Enhanced active protection technique for substrate minority carrier injection in Smart Power IC

Nitta, T.; Yoshihisa, Y.; Kuroi, T.; Hatasako, K.; Maegawa, Satoru; Onishi, Kazuma

doi:10.1109/ispsd.2012.6229059

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…Without going into details, minority carrier injection prevention [9], thermal-SOA evaluation/ improvement [10], FPMOS current drivability enhancement [11], and pulse stress evaluation to SOI devices [12] have contributed to size reduction and the increased reliability.…”

Section: Soi Device Technologymentioning

confidence: 99%

Past and Future Technology for Mixed Signal LSI

Hatasako

Nitta

Hane

et al. 2014

IEICE Trans. Electron.

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SUMMARYThis paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL transistor is one future device which enables 3D IC and chip shrinking technology.

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Section: Soi Device Technologymentioning

confidence: 99%

Past and Future Technology for Mixed Signal LSI

Hatasako

Nitta

Hane

et al. 2014

IEICE Trans. Electron.

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“…This is then a solution that designers do not normally use. In any case it is important to mention that some works have used TCAD as the main tool to develop protections for minority carriers injection in order to reduce the substrate cross-talk [3], [4]. Other options normally used to reduce the substrate parasitic couplings are based on technological modifications, like improved isolation structures or the use of Deep Trench Isolation (DTI) structures [5].…”

Section: Introductionmentioning

confidence: 99%

Substrate modeling to improve reliability of high voltage technologies

Stefanucci¹,

Buccella²,

Moursy³

et al. 2015

2015 IEEE 20th International Mixed-Signals Testing Workshop (IMSTW)

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In Smart Power ICs there is the need of new substrate models to be integrated in the design flow of power circuits. This work reports the latest results regarding the substrate modeling methodology based on three-dimensional lumped components extraction of diodes, resistors and contacts. The substrate network including lateral and vertical parasitic bipolar transistor can be automatically created from any chip layout including temperature and geometry variations. In such a way fast dc and transient analysis can be carried out in early design stages to improve reliability of high voltage ICs. Since the high variability and complexity on modern Smart Power technologies, a flexible model is required. This work discusses all the features related to technology variations. Circuit simulator results are then compared with TCAD simulations.

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