Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals

So, Keith

doi:10.1145/1344671.1344677

Cited by 5 publications

(3 citation statements)

References 35 publications

(37 reference statements)

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“…So [28] introduced a delay budgeting scheme to reduce the critical path delay of a circuit synthesized on an FPGA; since this is a post-processing step, it could improve the quality of results for all data points reported in Fig. 10 of this paper; however, it significantly increases the router runtime by a factor of at least 7× and also increases the memory footprint.…”

Section: B Fpga Routing Algorithmsmentioning

confidence: 99%

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Moctar¹,

Lemieux

Brisk

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Field programmable gate array (FPGA) routing is one of the most time consuming steps in a typical computer-aided design flow. The problem itself is similar to the NP-complete problem of computing a set of disjoint paths in a graph. The routing resource graph (RRG) that represents an FPGA routing network is necessarily large, and becomes even larger when modeling modern FPGAs that integrate sparse intracluster routing crossbars. This paper introduces two scalable heuristics that reduce the runtime and memory footprint of FPGA routing: 1) selective RRG expansion (SERRGE), which employs an application-specific memory manager that stores the RRG in a compressed form, and dynamically decompresses it as the router proceeds and 2) partial prerouting (PPR) locally routes all nets within each logic cluster, followed by a global routing stage to complete the routes. PPR and SERRGE converge faster than a traditional router using a fully expanded RRG. PPR runs faster and uses less memory than SERRGE, while SERRGE yields the highest clock frequencies among the three.Index Terms-Field programmable gate array (FPGA), routing, routing resource graph (RRG).

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Section: B Fpga Routing Algorithmsmentioning

confidence: 99%

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Moctar¹,

Lemieux

Brisk

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Rather than simply identifying a path as good or bad, we can identify whether or not a path is fast enough to be usable to achieve a particular timing goal. These extensions will demand time-sensitive tests (e.g., Wong et al [2007]) and time targets for nets (e.g., delay budget distribution [So 2008]).…”

Section: Variationmentioning

confidence: 99%

Choose-your-own-adventure routing

Rubin

DeHon

2011

ACM Trans. Reconfigurable Technol. Syst.

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Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. The fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable channel width, routes can tolerate 0.01% switch and wire defect rates, raising yield from essentially 0% to near 100%.

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“…These extensions will demand time-sensitive tests and time targets for nets (e.g. delay budget distribution [24]). …”

Section: Variationmentioning

confidence: 99%

Choose-your-own-adventure routing

Rubin

DeHon

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the intended operational characteristics. Without careful mitigation, component yield rates will fall, potentially negating the economic benefits of scaling. The fine-grained reconfigurability inherent in FPGAs is a powerful tool that can allow us to drop the stringent requirement that every device be fabricated perfectly in order for a component to be useful. To exploit inherent FPGA reconfigurability while avoiding full CAD mapping, we propose lightweight techniques compatible with the current single bitstream model that can avoid defective devices, reducing yield loss at high defect rates. In particular, by embedding testing operations and alternative path configurations into the bitstream, each FPGA can avoid defects by making only simple, greedy decisions at bitstream load time. With 20% additional tracks above the minimum routable channel width, routes can tolerate 0.01% switch defect rates, raising yield from essentially 0% to near 100%.

show abstract

Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals

Cited by 5 publications

References 35 publications

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars

Choose-your-own-adventure routing

Choose-your-own-adventure routing

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