Energy Savings via Dead Sub-Block Prediction

Abstract

Abstract-Cache memories have traditionally been designed to exploit spatial locality by fetching entire cache lines from memory upon a miss. However, recent studies have shown that often the number of sub-blocks within a line that are actually used is low. Furthermore, those sub-blocks that are used are accessed only a few times before becoming dead (i.e., never accessed again). This results in considerable energy waste since 1) data not needed by the processor is brought into the cache, and 2) data is kept alive in the cache longer than necessary.We propose the Dead Sub-Block Predictor (DSBP) to predict which sub-blocks of a cache line will be actually used and how many times it will be used in order to bring into the cache only those sub-blocks that are necessary, and power them off after they are touched the predicted number of times. We also use DSBP to identify dead lines (i.e., all sub-blocks off) and augment the existing replacement policy by prioritizing dead lines for eviction. Our results show a 24% energy reduction for the whole cache hierarchy when averaged over the SPEC2000, SPEC2006 and NAS-NPB benchmarks.

A survey of architectural techniques for improving cache power efficiency

“…without die-stacking) cache and also block-based and page-based 3D stacked DRAM cache designs. [19], [31], [39], [42], [45], [52], [53], [79] state-destroying [13], [20], [23]- [25], [29], [43], [70], [80]- [86] either or both [30], [41], [87], [88] Reconfig. granularity way-level [20], [52], [53], [56], [89]- [93] set-level (or bank-level) [43], [92] hybrid (set and way) level [23], [81], [94] cache block-level [13], [29], [31], [41], [42], [45], [78]- [80], [84], [88] cache sub-block level [86], cache color level [24]- [26] cache sub-array level [82] Reconfig.…”

“…[30], [31], [41], [45], [52], [53], [78], [86], [87] Basic property on Inclusion property of cache hierarchies [30] which ESTs work temporal locality [13], [29], [31], [41], [42], [45], [48], [52], [79], [80], [84], [86] varying working set size [23]- [26], [43], [81], [94], [95] What is turned-off Only data array (and not tag array) [29], [80], [96] both data and tag arrays (almost all others) Profiling: offline Offline (or compiler analysis) [41], [43], [45], [81], [93], [94], [97]- [100] or online online (almost all others) Thermal aware ESTs [88], [92], [93], [101], [102] ESTs for multi-cores/ [26], [27], [56], …”

Data Criticality in Network-On-Chip Design

“…3 This is visualized in Fig 4, where each area under the curve represents a subset of words that are assigned 3 We do not consider channel widths narrower than 4 bits. Logic overheads of routing and allocation and sideband signals make narrow channels unrealistic.…”

“…These focus on prefetching and cache power savings. Other techniques can identify when words and sub-blocks will no longer be used before eviction [1,3,19,23,28]. Kumar et al exploit dead words using variable block granularity to reduce cache energy [22].…”

Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management

“…Next time the line is fetched, the sub-blocks that are predicted not be accessed are switched-off (using the Gated Vdd scheme). Alvez et al [34] have extended and modified the design to predict when the accessed sub-blocks become dead. To implement this, they have included 2-bit usage counters for every sub-block (instead of a single bit).…”