Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration

Hsieh, Ming-Che; Wu, Sheng-Tsai; Wu, Chia‐Lin; Lau, John H.; Tain, Ra-Min; Lo, Wei‐Chung

doi:10.1109/esime.2011.5765764

Cited by 12 publications

(4 citation statements)

References 18 publications

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“…Fig. 3 shows its finite element model, which is pure hexahedral element meshed (one-eighth element-meshed model is shown due to symmetry characteristic) [19]. In the TSV model, Cu is treated as a temperature-dependent plastic material [20], whereas all [20] other materials are considered as an elastic material, including a temperature-dependent Young's modulus and CTE for silicon (Si).…”

Section: Nonlinear Thermal Stress Analyses For Tsvsmentioning

confidence: 99%

“…The thickness of die (TSV H ) is 50 μm, the thickness of SiO 2 passivation (SiO 2T ) is 0.5 μm, and the thickness of Cu seed layer (Seed T ) is 1 μm. The thickness of Cu pad (CuP T ) is 2 μm [19]. The employed dimension of TSV diameter, Cu pad size (CuP D ), and pitch for each case is listed in Table III.…”

Section: Nonlinear Thermal Stress Analyses For Tsvsmentioning

confidence: 99%

“…An electroplated Cu through-silicon-via (EP-Cu TSV) is simulated to evaluate the thermal stress distributions and interfacial delamination behavior. The finite element model of the EP-Cu TSV is designed as a TSV blanketed with SiO 2 passivation layer and EP by sputtered Cu as a seed layer to cover SiO 2 and then filled with EP-Cu [19]. Fig.…”

Section: Nonlinear Thermal Stress Analyses For Tsvsmentioning

confidence: 99%

“…For the purpose of realizing thermal stress distributions and interfacial ERR in TSVs, the 3-D finite element model of a symmetrical single inline TSV with redistribution layer has been constructed to be analyzed. Four kinds of interfacial cracks embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) are introduced to estimate the interfacial ERR using modified virtual crack closure technique (MVCCT) [15]- [19]. All the material properties are assumed to be linear elastic except for Cu TSV, which are treated as nonlinear material to have precise thermal stresses in this test vehicle.…”

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Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

Hsieh¹,

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO 2 ) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO 2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO 2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration. Index Terms-3-D IC integration, energy release rate, finite element analysis, modified virtual crack closure technique, TSV.

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Section: Nonlinear Thermal Stress Analyses For Tsvsmentioning

confidence: 99%

Section: Nonlinear Thermal Stress Analyses For Tsvsmentioning

confidence: 99%

Section: Nonlinear Thermal Stress Analyses For Tsvsmentioning

confidence: 99%

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confidence: 99%

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