2014
DOI: 10.1109/tcpmt.2013.2283503
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Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

Abstract: The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO 2 ) dielectric layer, the induced thermal stresses and strains can occ… Show more

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Cited by 18 publications
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