Energy optimization of multilevel cache architectures for RISC and CISC processors

Ko, Uming; Balsara, Poras T.; Nanda, Ashwini K.

doi:10.1109/92.678891

Cited by 55 publications

(25 citation statements)

References 11 publications

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“…Many researchers have proposed power-efficient cache designs, e.g., [28]. Compiler-directed techniques for minimizing power consumed by cache have also received significant attention in the research community [30], [40].…”

Section: Paper Organizationmentioning

confidence: 99%

Power optimization of variable voltage core-based systems

Hong¹,

Kirovski

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

193

142

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Abstract-The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrialstrength multimedia and communication applications. Index Terms-High-level synthesis, scheduling, synthesis for low power, system-on-a-chip (SOC).

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Section: Paper Organizationmentioning

confidence: 99%

Power optimization of variable voltage core-based systems

Hong¹,

Kirovski

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

193

142

View full text Add to dashboard Cite

show abstract

“…Current research is being focused on energy efficient cache architectures ( [1], [3], [5], [9]) and new reconfigurable caching techniques ( [2], [4], [8]). Since circuit level techniques are not able to single handedly provide solutions for achieving the above mentioned ends, higher levels of abstraction namely Algorithmic and Architectural levels [7] are being looked at with increasing interest.…”

Section: Introductionmentioning

confidence: 99%

DYNORA: a new caching technique

Srivatsan¹,

Sudarshan²,

Bhaskaran³

2003

Euromicro Symposium on Digital System Design, 2003. Proceedings.

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“…They successfully addressed the problem of the instruction overlap among traces that was present in the trace cache [6]. In [5] the authors investigated the energy dissipation in the bit array and the memory peripheral interface circuits. Taking these parameters into consideration, they optimized the performance and power dissipation in the cache.…”

Section: Previous Workmentioning

confidence: 99%

Predictive Line Buffer: A Fast, Energy Efficient Cache Architecture

Ali

Aboelaze

Datta

Proceedings of the IEEE SoutheastCon 2006

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Two of the most important factors in the design of any processor are speed and energy consumption. In this paper, we propose a new cache architecture that results in a faster memory access and lower energy consumption. Our proposed architecture does not require any changes to the processor architecture, it only assume the existence of a BTB. Using Mediabench, a benchmark used for embedded applications, Simplescalar simulator, and CACTI power simulator,we show that our proposed architecture consumes less energy, and have better memory access time, than many existing cache architectures.

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Energy optimization of multilevel cache architectures for RISC and CISC processors

Cited by 55 publications

References 11 publications

Power optimization of variable voltage core-based systems

Power optimization of variable voltage core-based systems

DYNORA: a new caching technique

Predictive Line Buffer: A Fast, Energy Efficient Cache Architecture

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