Energy Modeling of Software for a Hardware Multithreaded Embedded Microprocessor

Kerrison, Steve; Eder, Kerstin

doi:10.1145/2700104

Cited by 38 publications

(57 citation statements)

References 22 publications

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“…The XMOS XCore instruction-level energy model [9] is based on the original model by Tiwari et al However, it redefines the notion of base cost to be the power dissipated while the processor is idle and uses individual instruction costs, scaled by the level of concurrency in the processor's pipeline as well as a constant overhead to account for circuit state switching between instructions. Model characterisation was performed using a measurement setup and instruction loops similar to those originally proposed in Ref.…”

Section: Defining and Constructing An Energy Model At Isa Levelmentioning

confidence: 99%

Energy-Aware Software Engineering

Eder¹,

Gallagher

2017

ICT - Energy Concepts for Energy Efficiency and Sustainability

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A great deal of energy in Information and Communication Technology (ICT) systems can be wasted by software, regardless of how energy-efficient the underlying hardware is. To avoid such waste, programmers need to understand the energy consumption of programs during the development process rather than waiting to measure energy after deployment. Such understanding is hindered by the large conceptual gap from hardware, where energy is consumed, to high-level languages and programming abstractions. The approaches described in this chapter involve two main topics: energy modelling and energy analysis. The purpose of modelling is to attribute energy values to programming constructs, whether at the level of machine instructions, intermediate code or source code. Energy analysis involves inferring the energy consumption of a program from the program semantics along with an energy model. Finally, the chapter discusses how energy analysis and modelling techniques can be incorporated in software engineering tools, including existing compilers, to assist the energy-aware programmer to optimise the energy consumption of code.

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Section: Defining and Constructing An Energy Model At Isa Levelmentioning

confidence: 99%

Energy-Aware Software Engineering

Eder¹,

Gallagher

2017

ICT - Energy Concepts for Energy Efficiency and Sustainability

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“…Comparing communication costs to computation, profiling of the XS1-L series of processors [4] shows that instructions cause core energy consumption of in the range of 1.0-2.25 μJ at 400 MHz and 1 V, including static power and dependent upon the operations they perform. We can consider this to be 31-70 nJ per bit operated upon.…”

Section: Energy Measurementmentioning

confidence: 99%

Swallow: Building an Energy-Transparent Many-Core Embedded Real-Time System

Hollis

Kerrison

2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Swallow is a many-core platform of interconnected embedded real time processors with time-deterministic execution and a cache-less memory subsystem. Its largest current configuration is 480 × 32-bit processors. It is open-source, designed from the ground up to allow the exploration of flexibility, scalability and energy efficiency in large systems of embedded processors. Further, it enables the behavior of various structures of parallel programs to be explored. It is a proof of concept and design example for other potential systems of this kind. We present the energy transparency features and proportional energy scaling of the system that allows it to be expanded beyond hundreds of cores. We discuss the design choices, construction and novel network implementation of Swallow. Currently, the system provides up to 240 GIPS, with each core consuming 71-193 mW, dependent on workload. Its power per instruction is lower than almost all systems of comparable scale. We discuss the challenges associated with efficiently utilizing this system, particularly communication/computation ratios, and give recommendations for future systems and their software.

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“…It is a specialization of the generic resource analysis presented in [8] for programs written in a high-level C-based programming language, XC [9], running on the XMOS XS1-L architecture, that uses the instructionlevel energy cost models described in [3]. The analysis is general enough to be applied to other programming languages and architectures (see [4,5] for details).…”

Section: Energy Static Analysis As Inputmentioning

confidence: 99%

Trading-off Accuracy vs Energy in Multicore Processors via Evolutionary Algorithms Combining Loop Perforation and Static Analysis-Based Scheduling

Banković

Liqat

López-García

2015

Lecture Notes in Computer Science

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Abstract. This work addresses the problem of energy efficient scheduling and allocation of tasks in multicore environments, where the tasks can permit certain loss in accuracy of either final or intermediate results, while still providing proper functionality. Loss in accuracy is usually obtained with techniques that decrease computational load, which can result in significant energy savings. To this end, in this work we use the loop perforation technique that transforms loops to execute a subset of their iterations, and integrate it in our existing optimisation tool for energy efficient scheduling in multicore environments based on evolutionary algorithms and static analysis for estimating energy consumption of different schedules. The approach is designed for multicore XMOS chips, but it can be adapted to any multicore environment with slight changes. The experiments conducted on a case study in different scenarios show that our new scheduler enhanced with loop perforation improves the previous one, achieving significant energy savings (3f % on average) for acceptable levels of accuracy loss.

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Energy Modeling of Software for a Hardware Multithreaded Embedded Microprocessor

Cited by 38 publications

References 22 publications

Energy-Aware Software Engineering

Energy-Aware Software Engineering

Swallow: Building an Energy-Transparent Many-Core Embedded Real-Time System

Trading-off Accuracy vs Energy in Multicore Processors via Evolutionary Algorithms Combining Loop Perforation and Static Analysis-Based Scheduling

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