Swallow: Building an Energy-Transparent Many-Core Embedded Real-Time System

Hollis, Simon; Kerrison, Steve

doi:10.3850/9783981537079_0399

Cited by 5 publications

(6 citation statements)

References 8 publications

(8 reference statements)

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“…Many other papers present different schemes to address power reduction using different simulators and methods for voltage and frequency scaling. Some of these papers addressed other issues such as scalability, memory hierarchy, thermal issues, and process variations [8], [11], [24], [39], [41]- [54].…”

Section: Related Workmentioning

confidence: 99%

“…For instance, Sniper/McPAT [22] is a power, area and timing model that is combined with a multicore simulator for application and architecture development. Others, such as [9], [23], and [24], target low power and/or speed exploration and modelling. However, a holistic simulation environment that includes the aforementioned factors is needed.…”

Section: Introductionmentioning

confidence: 99%

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Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

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In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

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“…In multi-threaded code, consolidating all read-writes to or from disk to a single thread can reduce disk contention and consequent disk-head thrashing [39]. Furthermore, knowledge of the relative communication distances for inter-core communication can be used to place frequently communicating threads close to each other [40], thus reducing communication energy costs.…”

Section: Data and Communication Efficiencymentioning

confidence: 99%

“…The xCORE architecture is highly configurable both in terms of the number of cores and their interconnection. The choice and configuration are guided by an energy model applied to proposed solutions, taking into account thread communication energy costs in a given configuration, as described in more detail in [40].…”

Section: Embedded System Development On Xcorementioning

confidence: 99%

Energy-Aware Software Engineering

Eder¹,

Gallagher

2017

ICT - Energy Concepts for Energy Efficiency and Sustainability

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A great deal of energy in Information and Communication Technology (ICT) systems can be wasted by software, regardless of how energy-efficient the underlying hardware is. To avoid such waste, programmers need to understand the energy consumption of programs during the development process rather than waiting to measure energy after deployment. Such understanding is hindered by the large conceptual gap from hardware, where energy is consumed, to high-level languages and programming abstractions. The approaches described in this chapter involve two main topics: energy modelling and energy analysis. The purpose of modelling is to attribute energy values to programming constructs, whether at the level of machine instructions, intermediate code or source code. Energy analysis involves inferring the energy consumption of a program from the program semantics along with an energy model. Finally, the chapter discusses how energy analysis and modelling techniques can be incorporated in software engineering tools, including existing compilers, to assist the energy-aware programmer to optimise the energy consumption of code.

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“…Moreover, the absence of performance-enhancing complexity at the hardware level, such as caches, make them ideal for critical applications. We base our choice of the Xcore processor among other more popular architectures used for IoT applications, such as the ARM Cortex-M series [3], on the fact that the Xcore is a time deterministic multi-threaded architecture that can be extended to many-core systems [4], allowing for a variety of design space exploration choices. Our SRA uses an ISA multi-threaded energy model for the Xcore introduced in [5].…”

Section: Introductionmentioning

confidence: 99%

Energy Transparency for Deeply Embedded Programs

Georgiou

Kerrison

Chamski³

et al. 2017

ACM Trans. Archit. Code Optim.

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Energy transparency is a concept that makes a program's energy consumption visible, from hardware up to software, through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, and help both programmers and operating systems make energy-aware decisions. In this paper, we focus on deeply embedded devices, typically used for Internet of Things (IoT) applications, and demonstrate how to enable energy transparency through existing Static Resource Analysis (SRA) techniques and a new target-agnostic profiling technique, without hardware energy measurements. Our novel mapping technique enables software energy consumption estimations at a higher level than the Instruction Set Architecture (ISA), namely the LLVM Intermediate Representation (IR) level, and therefore introduces energy transparency directly to the LLVM optimizer. We apply our energy estimation techniques to a comprehensive set of benchmarks, including single- and also multi-threaded embedded programs from two commonly used concurrency patterns, task farms and pipelines. Using SRA, our LLVM IR results demonstrate a high accuracy with a deviation in the range of 1% from the ISA SRA. Our profiling technique captures the actual energy consumption at the LLVM IR level with an average error of 3%.Comment: 33 pages, 7 figures. arXiv admin note: substantial text overlap with arXiv:1510.0709

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Swallow: Building an Energy-Transparent Many-Core Embedded Real-Time System

Cited by 5 publications

References 8 publications

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Energy-Aware Software Engineering

Energy Transparency for Deeply Embedded Programs

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