Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design - ISLPED '08 2008
DOI: 10.1145/1393921.1393941
|View full text |Cite
|
Sign up to set email alerts
|

Energy harvesting photodiodes with integrated 2D diffractive storage capacitance

Abstract: Integrating photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, low-cost energy harvesting wireless systems. To further explore the tradeoffs between optical efficiency and capacitive energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in TSMC's 90 nm CMOS technology. Transient effects from interfacing the photodiodes with switching regulators were examined. A quantitative comparison b… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
10
0

Year Published

2009
2009
2015
2015

Publication Types

Select...
4
2
1

Relationship

2
5

Authors

Journals

citations
Cited by 8 publications
(10 citation statements)
references
References 33 publications
(32 reference statements)
0
10
0
Order By: Relevance
“…T is the ambient temperature, expressed in K. The factor n is the emission (or ideality) coefficient, which equals 1 for an ideal diode. Although it is possible to build a PV cell using CMOS technology, it is not simple to integrate PV cells with other circuits in the same die, in order to obtain a complete system on chip (SoC) [68,69]. The PV cell causes a positive voltage in the substrate, thus causing a possible latch-up condition in the die.…”
Section: Lightmentioning
confidence: 99%
“…T is the ambient temperature, expressed in K. The factor n is the emission (or ideality) coefficient, which equals 1 for an ideal diode. Although it is possible to build a PV cell using CMOS technology, it is not simple to integrate PV cells with other circuits in the same die, in order to obtain a complete system on chip (SoC) [68,69]. The PV cell causes a positive voltage in the substrate, thus causing a possible latch-up condition in the die.…”
Section: Lightmentioning
confidence: 99%
“…Because the average power of circuits for sensor applications can be made very low due to low duty cycle and aggressive application of clock gating, power-down modes, and leakage reduction, it is possible to devote a fraction of die area to energy harvesting -thus integrating the power source into the chip itself. The simplest way to do this is to use CMOS passive pixels (similar to imager pixels) as photovoltaic cells to harvest solar energy [5], [6]. The metal interconnect layers on the chip can be exploited as capacitance to store the harvested energy, although at low energy density compared to off-chip ultracapacitors.…”
Section: Integrated Solar Energy Harvestingmentioning
confidence: 99%
“…Figure 3 shows a test chip fabricated to explore this idea using a number of test structures with different diffuser patterns. The optimal diffuser increases the range of incident angles which could generate 200mV from 0 -45 to 0 -60 [6]. For 20kLux incident light intensity, photodiodes in 0.35µm digital CMOS and 90nm digital CMOS have been shown to deliver output power of 225µW/mm 2 and 325µW/mm 2 , respectively.…”
Section: Integrated Solar Energy Harvestingmentioning
confidence: 99%
“…Increased system integration has allowed solar energy harvesters, in the form of passive photodiodes, to be implemented on the same silicon die as active circuitry, which can be powered by the harvested energy. These integrated photodiodes [1], [2] are modeled after a passive pixel architecture [3], which can form the basis for CMOS imagers. Previous works have outlined the use of environmental energy-harvesting for powering wireless systems [4]- [23].…”
mentioning
confidence: 99%
“…A 2-D photodiode structure, consisting of p-diffusion fingers implanted in an n-well, was implemented. Vertical parallel plate storage capacitance using metal routing layers can be constructed on top of the fingers, forming an optical diffraction grating [2]. Metal density design rules are becoming stricter as technology continues to scale in modern CMOS processes.…”
mentioning
confidence: 99%