Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, Kimiyoshi; Akaike, Junya; Akiba, Sosuke; Kudo, Masatoshi; Amano, Hideharu; Ikezoe, Takeharu; Hiraga, Keizo; Shuto, Yusuke; Yagami, K.

doi:10.1109/nvmsa.2018.00023

Cited by 13 publications

(23 citation statements)

References 8 publications

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“…A typical Flip-Flop (FF) is a volatile device whose value is lost after the power is turned off. A Non-Volatile Flip-Flop (NVFF) [9]- [15] consists of an FF and a non-volatile element. The data stored in the FF is volatile, and the data stored in the non-volatile element is non-volatile.…”

Section: Non-volatile Flip-flop (Nvff)mentioning

confidence: 99%

“…On the other hand, the NVFF stores the FF's value into the nonvolatile element only when a store operation is performed. Since a store operation fails with a certain probability [15], an SoC with many NVFFs must have a function to verify whether each NVFF has successfully performed a store operation. Therefore, a VR-NVFF [15] is useful for such SoCs because it can perform a verify operation that compares whether the non-volatile element's value is equal to the FF's value.…”

Section: Non-volatile Flip-flop (Nvff)mentioning

confidence: 99%

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Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Nakabeppu

Yamasaki

2023

IEICE Trans. Electron.

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It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

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Section: Non-volatile Flip-flop (Nvff)mentioning

confidence: 99%

Section: Non-volatile Flip-flop (Nvff)mentioning

confidence: 99%

Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Nakabeppu

Yamasaki

2023

IEICE Trans. Electron.

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“…The typical method of detecting write errors is to copy the data written to the MTJ devices to a latch for verification (balloon latch), and then compare it to the value held in the FF. 27) In this operation, the balloon latch copies the stored data in the NVM block by sensing the voltage difference, which is obtained by flowing the read current to two MTJ devices and amplifying it by a cross-coupled loop in the circuit. Based on this operating principle, the conventional balloon latch can only read the complementary state of the two MTJ devices, that is, the state in which both MTJ devices are correctly written or in which both MTJ elements have failed to write (differential-mode error state).…”

Section: Vulnerability Of Conventional Nvffmentioning

confidence: 99%

“…25,26) However, traditional ECC techniques, such as adding parity bits, are not suitable for nonvolatile logic LSIs, which have a distributed NVM over the logic plane. Examples of highly reliable NVFF configurations that have a function to detect write errors in NVM have been proposed; 27) however, they support only a subset of possible error conditions and are not sufficient to achieve this objective.…”

Section: Introductionmentioning

confidence: 99%

Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Natsui

Yamagishi

Hanyu

2021

Jpn. J. Appl. Phys.

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Nonvolatile flip-flop (NVFF) is an important component for implementing an energy-efficient logic large-scale integration (LSI) circuit that utilizes nonvolatile memory (NVM) function of magnetic tunnel junction (MTJ) devices. NVFF must be highly reliable in data store and restore operations for nonvolatile power gating. This study proposes an NVFF that can detect arbitrary errors occurring when storing data to the embedded NVM caused by the stochastic behavior of MTJ devices. The performance evaluation results show that the proposed NVFF can detect arbitrary error conditions, including the unsupported condition in the previously proposed reliable NVFF, while maintaining comparable performance to a conventional condition in normal flip-flop operations.

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“…The clock framework, which comprises of the clock dissimation and consecutive components (flip-flops), is a standout amongst the most power expanding segments in a VLSI framework. [1]. By using clock drivers the chip power is delivered.…”

Section: Introductionmentioning

confidence: 99%

Design A High Speed Spin-Torque Transfer Magnetic Tunnel Junction (Stt-Mtj) Non-Volatile Flip-Flops Based On Memory

Krishna¹,

Santhosh²,

Indira³

2019

IJITEE

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Basically, in low power applications, the energy should be harvested depend on the frequent interruptions. In this paper we proposed the design of spin-transfer torque magnetic tunnel junctions (STT-MTJs) non volatile based on flip flops based memory. The main intent of non volatile is to address the state of system by saving the memory. By using STT-MTJs based flip flop, high energy consumption will be obtained and there will be backup of the system. In CMOS the flip flop will used standard magnetic MRAM technology. The main intent of magnetic tunnel junctions is to store the data. The proposed non volatile flip flop will determine the delay and energy. Logic circuits are enabled using non volatility and this will reduce the start up latency. This start up latency ranges from micro seconds to hundred pico seconds. Here the information is stored using non volatile logic of memory. This process is done on pre chip basis. Hence compared to existed system, the proposed system gives effective results.

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Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Cited by 13 publications

References 8 publications

Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Non-Stop Microprocessor for Fault-Tolerant Real-Time Systems

Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Design A High Speed Spin-Torque Transfer Magnetic Tunnel Junction (Stt-Mtj) Non-Volatile Flip-Flops Based On Memory

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