Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors

Abstract

Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1-1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features 37% lower energy per FFT/IFFT computation than the sync approach but with 10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35-m CMOS process) can be operated at 1.0 V and dissipates 93 nJ.

Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT

“…Tab. III therefore provides a design comparison based on three metrics -Benefit Product [15] and eτ 2 using Baireddy as the reference, and Normalized FFTs per Energy [14]. Benefits Product is the product of the area, energy, and execution time.…”

“…The Normalized FFTs per Energy metric largely disregards performance. Those results are normalized to the 350nm node to produce the same values as reported in [14].…”

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips

“…Instead, an asynchronous-logic (async) methodology could be in part adopted to circumvent such data synchronization issue. The basic premise is that async circuits are essentially self-timed circuits by using async handshake protocols [3], [4] to synchronize digital operations.…”

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic

“…Instead, an asynchronous-logic (async) methodology could be fully or in part adopted to alleviate such data synchronization issues. The basic premise is that async circuits are essentially self-timed circuits by using async handshake protocols [3], [4] to synchronize digital operations. Consequently, async circuits are more advantageous in accommodating the effects of PVT variations [5].…”