Abstract-Asynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity. However, asynchronous design styles are largely incompatible with clocked CAD, which has prevented wide-scale adoption. The key incompatibility is timing. Thus most commercial work relies on custom CAD or untimed delay-insensitive design methodologies. This paper proposes a new methodology, based on formal verification and relative timing, to create and prove correct necessary constraints to support asynchronous design with traditional clocked CAD. These constraints support timing driven synthesis, place and route, and behavior and timing validation of fully asynchronous designs using traditional clocked CAD flows. This flow is demonstrated through a simple example pipeline in IBM's 65nm process showing the ability to retarget the design for improved power and performance.
Abstract-A case study exploring multi-frequency design is presented for a low energy and high performance FFT circuit implementation. An FFT architecture with concurrent data stream computation is selected. An asynchronous and synchronous implementations for a 16-point and a 64-point FFT circuit were designed and compared for energy, performance and area. Both versions are structurally similar and are generated using similar ASIC CAD tools and flows. The asynchronous design shows a benefit of 2.4×, 2.4× and 3.2× in terms of area, energy and performance respectively over its synchronous counterpart. The circuit is further compared with other published designs and shows 0.4×, 4.8× and 32.4× benefit with respect to area, energy and performance.
Abstract-Universal Asynchronous Receiver Transmitter (UART) implements serial communication between peripherals and remote embedded systems. The UART protocol is defined based on fixed frequencies with a sampling method to achieve robustness under reasonable frequency variations between systems. Such design specifications are natural for clocked domains. This work investigates whether this simple clocked hardware protocol can be advantageously implemented using asynchronous design techniques. A full duplex clocked and asynchronous UART are implemented and compared. The asynchronous design results in average power of about onefourth that of the clocked design under standard operating modes.
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