Energy-efficient switching scheme for SAR ADC with only two reference voltages

Liu, Shubin; Han, Haolin; Ding, Ruixue; Zhu, Zhangming

doi:10.1007/s10470-018-1339-6

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…Te MSB capacitor is arranged as the conventional binary-weighted technique, while the next 9 bits are divided into two-stage subarray capacitors that replace the big-weight capacitors with 7 equal capacitors. Several works have adopted special arrangements for capacitor array technique [54][55][56][57][58][59][60][61]. Te asymmetric capacitors technique [54] is shown in Figure 17, where MSB on the higher side of the capacitor array is removed.…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…In [57], the reduction of energy and area has been accomplished by employing goblet architecture for the capacitor array without the need for extra reference voltage. All capacitors can be pulled up and down levels as shown in Figure 20.…”

Section: Capacitive Dac Array (Cdac)mentioning

confidence: 99%

“…Tese schemes include the two-level, three-level and four-level voltage switching schemes. Two-level voltage switching schemes have been used in [41,44,57,[69][70][71][72][73] to improve the power consumption and enhance the stability and accuracy of CDAC. Higher precision and linearity can be obtained with lower average switching energy by employing two-level voltages.…”

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

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Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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