Energy efficient proactive thermal management in memory subsystem

Ayoub, Raid; Indukuri, Krishnam Raju; Rosing, Tajana

doi:10.1145/1840845.1840884

Cited by 18 publications

(11 citation statements)

References 13 publications

(14 reference statements)

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“…Hanson et al [8] analyze the thermal efficiency of performing memory throttling on server systems. Ayoub et al [1] propose a thermal management policy for the DRAMs by utilizing proactive page allocation. For reducing DRAM power, Deng et al [5] propose to adjust the V-F level of DRAMs, and coordinate the CPU and DRAM system DVFS in server systems to achieve high power efficiency [4].…”

Section: Related Workmentioning

confidence: 99%

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs

Chen

Yang

Lin

et al. 2015

Proceedings of the 2015 Conference on Research in Adaptive and Convergent Systems

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Chip-Multiprocessors (CMPs) with 3D-stacked DRAMs is promising for solving the memory wall problem, but the high power density makes 3D ICs frequently operate at or near the thermal limit. System hot spot of a CMP with 3D-stacked DRAMs is usually in DRAMs that are in the layers farthest from the heat sink. Heat from DRAMs and cores are all accumulated in DRAMs. Therefore, existing thermal managements for 3D ICs all perform thermal control on cores only because lowering the power-level of cores can also lower DRAM access frequency. However, as the power consumption of single DRAM access increases with the number of DRAM stacks and the width of the vertical links, the instantaneous DRAM accesses may easily overheat the system. So, in addition to lowering the access frequency of DRAMs, reducing the power consumption per DRAM access is also crucial. In this paper, we characterize the thermal and performance behavior of the target architecture when the voltage and frequency levels of cores and DRAMs are synergistically controlled. We also evaluate the thermal and performance behavior of existing thermal control methods that can be applied to the target architecture. The insights provided by the characterizations presented in this paper are important for developing an effective thermal management policy for CMPs with 3D-stacked DRAMs. Our results show that, synergistically controlling the voltage-frequency levels of cores and DRAMs does achieve higher thermal efficiency than controlling cores only.

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Section: Related Workmentioning

confidence: 99%

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs

Chen

Yang

Lin

et al. 2015

Proceedings of the 2015 Conference on Research in Adaptive and Convergent Systems

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“…Utilizing on-line monitoring, Christoforakis et al (2015) propose a response mechanism using a distributed power management algorithm for Field Programmable Gate Array (FPGA) to evenly reduce and normalize power transients and achieve a power-and thermal-aware coherent system. Ayoub et al (2010) presented a DTM mechanism for memory subsystems which intelligently allocates workload pages to few memory units and powers down the rest of the memory.…”

Section: Dynamic Thermal-aware Management Methodsmentioning

confidence: 99%

On-Chip Dynamic Resource Management

Miele

Kanduri²,

Moazzemi³

et al. 2019

FNT in Electronic Design Automation

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The need for dynamic resource management has shadowed the exponential growth of on-chip transistor capacity, and the challenge is accentuated by the heterogeneity of resources, and the bewildering variety of constraints and requirements of applications, platforms and users. The field has started with a few research papers in the early 1990s but has grown today to over hundred yearly publications, leading to an accumulated body of literature presumable far above 1000 papers. We focus on the dynamic (run-time) management of onchip resources and mostly ignore design-time techniques and off-chip resources of larger electronic systems. Moreover, we do not attempt a complete review of all published work on the topic. Rather, this survey provides a structured review and discussion of the state of the art and is divided along the primary objectives of resource management techniques: performance, power, reliability and quality of service, each

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“…Smart performance and power modeling can reduce the power leakage and limit temperature increase which can improve performance and power consumption [17]. Thermal management became a prominent challenge in dark silicon era [18]. Furthermore, [19] proposes a thermal-aware computation in nano scale technologies.…”

Section: B Temperaturementioning

confidence: 99%

Trends in On-chip Dynamic Resource Management

Moazzemi¹,

Kanduri²,

Juhász³

et al. 2018

2018 21st Euromicro Conference on Digital System Design (DSD)

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The Complexity of emerging multi/many-core architectures and diversity of modern workloads demands coordinated dynamic resource management methods. We introduce a classification for these methods capturing the utilized resources and metrics. In this work, we use this classification to survey the key efforts in dynamic resource management.We first cover heuristic and optimization methods used to manage resources such as power, energy, temperature, Qualityof-Service (QoS) and reliability of the system. We then identify some of the machine learning based methods used in tuning architectural parameters in computer systems. In many cases, resource managers need to enforce design constraints during runtime with a certain level of guarantee. Hence, we also study the trend in deploying formal control theoretic approaches in order to achieve efficient and robust dynamic resource management.

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Energy efficient proactive thermal management in memory subsystem

Cited by 18 publications

References 13 publications

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs

On-Chip Dynamic Resource Management

Trends in On-chip Dynamic Resource Management

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