Energy efficient Phase Change Memory based main memory for future high performance systems

Abstract

Phase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As the need for high-density memory increases, DRAM has proven to be less attractive from the point of view of scaling and energy consumption. PCM-only memories suffer from latency issues, high write energy, and the problem of limited write endurance. Research in this domain has focused mainly on using various hybrid memory configurations to address these shortcomings. A commodity DRAM module as a cache for PCM memory has emerged as a potential solution. But this method requires use of a separate memory controller and is unable to achieve better performance than a DRAM-only based memory at low energy.We propose a PCM based main memory system design using a small, embedded DRAM (eDRAM) cache to replace the row buffers in the PCM memory chip. This reduces the high latencies of PCM and the energy consumption of the main memory system. Our methodology also eliminates the need for separate memory controllers. Through simulation results, we show competitive performance by reducing average memory access time of a slow PCM based memory and significant energy reductions against a DDR3 commodity DRAM memory system of similar storage size. Our proposed system is highly energy efficient and provides 35.02%improvement in EDP over a DRAM-only system. Our system consumes less energy than the state-of-the-art PCM hybrid system using a commodity DRAM cache.

Evaluating STT-RAM as an energy-efficient main memory alternative

“…Instead, PCRAM and STT-RAM appear to be the competing alternatives to DRAM. Of these, PCRAM promises substantial density benefits (at least 2-4X over DRAM today), and it has been studied extensively to replace or augment DRAM in building a higher capacity and more scalable main memory system [5], [30], [49], [52], [66], [64]. However, it is both much slower (about 2-4X read, 10-100X write) and much more power hungry (about 2-4X read, 10-50X write), compared to DRAM [30], [50], [55], [61].…”

Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression

“…Embedding a large (e)DRAM device is not an impractical configuration. In prior studies, 64MB (or even larger) (e)DRAM devices have been used [Bheda et al 2011;Chang et al 2013]. Moreover, the recently announced IBM POWER8 processor architecture has 96MB of (e)DRAM on-chip cache [IBM 2013], while Intel is considering 128MB of (e)DRAM in the upcoming Haswell GT3e variant [Kurd et al 2014].…”

“…-It has low power consumption, consuming approximately 1/3 of the equivalent DRAM power consumption when in read operating mode [Bheda et al 2011;Dhiman et al 2009], and almost zero consumption when in idle state. Moreover, unlike DRAM, no refresh is required.…”

A Software-hardware Collaborating Framework for Wear Leveling on Phase Change Memory

“…[11] introduced a PCM-aware swap algorithm, which uses a global write counter as swap condition and chose the target page randomly. [19] designed a PCM based main memory system embedding small DRAM as cache to achieve low energy consumption as well as low access latency. The small DRAM buffer was also used in [20].…”