Energy-efficient NoC for best effort communication

Abstract

A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for Multi-Processor System-onChip (MPSoC) architectures. In an earlier paper we proposed a energy-efficient reconfigurable circuit-switched NoC to reduce the energy consumption compared to a packetswitched NoC. In this paper we investigate a chordal slotted ring and a bus architecture that can be used to handle the best-effort traffic in the system and configure the circuitswitched network. Both architectures are compared on their latency behavior and power consumption. At the same clock frequency, the chordal ring has the major benefit of a lower latency and higher throughput. But the bus has a lower overall power consumption at the same frequency. However, if we tune the frequency of the network to meet the throughput requirements of control network, we see that the ring consumes less energy per transported bit.

Efficient dynamic reconfiguration for multi-context embedded FPGA

“…The interconnection network presented in [5] consists in a set of reconfigurable circuit-switched routers interconnected by links. One router is composed of five 16-bit bi-directional ports connected through a 16x20 fully connected crossbar.…”

Energy Model of Networks-on-Chip and a Bus

“…The second network is a guaranteed throughput circuitswitched router [8] in combination with a separate best-effort network [9]. By using dedicated techniques for both types of traffic (BE and GT) we can reduce the total area and power consumption.…”

“…The best-effort traffic is handled via a separate ring network [9] that can transport packets (16 bit data, 16 bit address) to all the processing tiles and circuit-switched routers. Via the configuration interface of the circuit-switched router a single best-effort packet can configure 1 lane.…”

Energy characteristic of a processor allocator and a network-on-chip

“…Finally, the energy consumed on the physical channels between tiles in [pJ/bit] is E 2D−mesh L bit = 0.57 for k-ary 2-mesh and E 2D−torus L bit = 0.75 for a k-ary 2-cube topology. The research by Wolkotte et al (2005a) is extended in another work (Wolkotte et al, 2005b), where gate level power simulation of a VC router is performed. The router routes packets according to the DOR scheme.…”

“…(3), E R bit and E L bit are constants for a given design. Wolkotte et al (2005a) presented a performance analysis of wires. The estimated…”