Energy Model of Networks-on-Chip and a Bus

Wolkotte, P.T.; Smit, Gerard J. M.; Kavaldjiev, N.K.; Becker, Jürgen

doi:10.1109/issoc.2005.1595650

Cited by 55 publications

(26 citation statements)

References 6 publications

(9 reference statements)

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“…There are also NoC power modeling and estimation work. [19] is an attempt on deriving the energy model of NoC based multicore chips and made comparison to a traditional bus. [20] presents a high level power estimation methodology for a NoC router to enable power exploration at system level.…”

Section: Related Workmentioning

confidence: 99%

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Kondo

Nakada

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYNetworks-on-Chip (or NoCs, for short) play important roles in modern and future multi-core processors as they are highly related to both performance and power consumption of the entire chip. Up to date, many optimization techniques have been developed to improve NoC's bandwidth, latency and power consumption. But a clear answer to how energy efficiency is affected with these optimization techniques is yet to be found since each of these optimization techniques comes with its own benefits and overheads while there are also too many of them. Thus, here comes the problem of when and how such optimization techniques should be applied. In order to solve this problem, we build a runtime framework to throttle these optimization techniques based on concise performance and energy models. With the help of this framework, we can successfully establish adaptive selections over multiple optimization techniques to further improve performance or energy efficiency of the network at runtime.

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Section: Related Workmentioning

confidence: 99%

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Kondo

Nakada

et al. 2016

IEICE Trans. Inf. & Syst.

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“…At first, Scientists study specific hardware components of computer, in [20], the author found the power dissipation in micro-process. Then it goes to the energy model, in [21], [22][23], they built energy model to help research and they made the prove more reasonable. Nowadays, people are more interested in energyaware software and system [24] design.…”

Section: B Power-aware Strategymentioning

confidence: 99%

Fine-grained power management using process-level profiling

Cai

Shi

2012

Sustainable Computing: Informatics and Systems

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“…In this evaluation, we use the values already estimated in the energy model proposed in 35 in which the average amount of energy required for a single bit to pass a switch is equal to 0.9776pJ/bit and the average amount of energy required for a single bit to cross a link is (0.39 + 0.12L ) pJ/bit, where L is the length of the link . To calculate L , we consider that the link between each core and its corresponding switch is of length 1mm.…”

Section: Energymentioning

confidence: 99%

Performance evaluation and design tradeoffs of on-chip interconnect architectures

Bakhouya

Suboh

Gaber

et al. 2011

Simulation Modelling Practice and Theory

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Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely based on simulations, which become computationally expensive, especially for large-scale NoCs. In this paper, a Network Calculusbased methodology is presented to analyze and evaluate the performance and cost metrics, such as latency and energy consumption. The 2D Mesh, Spidergong, and WK-recursive on-chip interconnect architectures are analyzed using this methodology and results are compared with those produced using simulations. The values obtained by simulations and by analysis show similar trends in the same order of magnitude. Furthermore, WK outperforms the other on-chip interconnects in all considered metrics.

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Energy Model of Networks-on-Chip and a Bus

Abstract: Abstract-

Cited by 55 publications

References 6 publications

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Fine-grained power management using process-level profiling

Performance evaluation and design tradeoffs of on-chip interconnect architectures

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