Energy-efficient interconnect via Router Parking

Abstract

The increase in on-chip core counts in Chip MultiProcessors (CMPs) has led to the adoption of interconnects such as Mesh and Torus, which consume an increasing fraction of the chip power. Moreover, as technology and voltage continue to scale down, static power consumes a larger fraction of the total power; reducing it is increasingly important for energy proportional computing. Currently, processor designers strive to send under-utilized cores into deep sleep states in order to reduce idling power and improve overall energy efficiency. However, even in state-of-the-art CMP designs, when a core goes to sleep the router attached to it remains active in order to continue packet forwarding. In this paper, we propose Router Parking -selectively power-gating routers attached to parked cores. Router Parking ensures that network connectivity is maintained, and limits the average interconnect latency impact of packet detouring around parked routers. We present two Router Parking algorithms -an aggressive approach to park as many routers as possible, and a conservative approach that parks a limited set of routers in order to keep the impact on latency increase minimal. Further, we propose an adaptive policy to choose between the two algorithms at run-time. We evaluate our algorithms using both synthetic traffic as well as real workloads taken from SPEC CPU2006 and PARSEC 2.1 benchmark suites. Our evaluation results show that Router Parking can achieve significant savings in the total interconnect energy (average of 32%, 40% and 41% for the synthetic, SPEC CPU2006, and PARSEC 2.1 workloads, respectively).

Power-Aware NoCs through Routing and Topology Reconfiguration

“…Even though frequent decisions to power-gate components are made locally at each router, Panthre's novel reconfiguration solution ensures uninterrupted full connectivity and deadlock-freedom of the NoC topology globally at runtime. Panthre, by construction, is also free of reconfiguration-induced routing deadlock [9], thus eliminating the need for costly deadlock-recovery protocols [2,14]. Finally, it can reconfigure frequently without ever interrupting normal network operation.…”

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

“…Power gating has been extensively explored within the context of NoCs, in order to reduce the leakage power [16,7], to improve the reliability of some part of the architecture [21,22], or both [20]. We categorize the power-gating techniques based on their operational granularity, i.e., either at the router-level (entire router switched off), or at the buffer-level (only individual buffers are switched off).…”

“…Router Parking (RP) [16] is a methodology to save power with minimum performance loss, by ''parking'' routers associated with sleeping cores and pro-actively aggregating traffic to the active routers. A new component, the centralized Fabric Manager (FM), is introduced to the architecture to collect information about the traffic in the NoC.…”

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

“…A router parking method is proposed in [3] to power-gate routers when the connected core is idle, but it needs to flush private caches before turning off routers, which may cause serious performance decrease. The node-router disconnection referred to by [12] severely limits power-gating being effectively used in on-chip routers due to the limitation of break-even time, long wake-up delay.…”

“…In the simulation of Samih et al [3], the leakage power increases rapidly, from 11.2% of the total router powerconsumption in the 65 nm technology to 33.6% in the 32 nm technology, when working at 1.1 V voltage and 2.0 GHz frequency.…”