Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication

Maheshwari, Sachin; Bartlett, V.A.; Kale, I.

doi:10.1016/j.vlsi.2018.04.002

Cited by 15 publications

(7 citation statements)

References 11 publications

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“…Using our home-grown cell library, the structural model of a 16-bit CRC circuit for a 16-bit message word was successfully verified. The block diagram and the working of the 16-bit CRC circuit are given in [12]. Similar simulation setups were maintained for both the SPICE and VHDL analysis for uniformity and proper comparability.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…5) The reliability and robustness of the proposed modelling approach were verified for 16-bit CRC circuit [12].…”

Section: A Contributions Of This Papermentioning

confidence: 98%

“…The operation of the adiabatic logic gates is complex to model accurately due to the two cross-coupled inverters forming a latch [12], which retains the last value stored on the two output nodes. For example: if the mutually exclusive adiabatic inputs are both at logic '0' (indicating an invalid state), the adiabatic outputs will retain the last value stored, thus making it difficult to debug in large-scale systems, especially in the case when functionally, logic '1'and '0' is expected on the two output nodes.…”

Section: Modelling Invalid Inputsmentioning

confidence: 99%

“…In the same line of thinking the leakage power is another concern for deep sub-micron technologies. Moreover, the Non-Adiabatic Losses (NAL) arising due to the threshold voltage degradation causes energy to increase and is different for different adiabatic logic families [5], [12]. At the functional level, all the above effects will not alter the functionality unless wrong inputs/connections are provided.…”

Section: E Bennett Clocking Compatibility and Other Effectsmentioning

confidence: 99%

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A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Maheshwari

Bartlett

Kale

2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a Hardware Description Language (HDL) based modelling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit's invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit Cyclic Redundancy Check (CRC) circuit. The system modelled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems.

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Section: Simulation Resultsmentioning

confidence: 99%

“…5) The reliability and robustness of the proposed modelling approach were verified for 16-bit CRC circuit [12].…”

Section: A Contributions Of This Papermentioning

confidence: 98%

Section: Modelling Invalid Inputsmentioning

confidence: 99%

Section: E Bennett Clocking Compatibility and Other Effectsmentioning

confidence: 99%

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A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Maheshwari

Bartlett

Kale

2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…For more than two decades, adiabatic logic has been widely studied and various adiabatic logic families have been proposed [21]- [26]. Single phase [21] and 2-phase [22] adiabatic logic families are less complex due to the low complexity of powerclock generator but, have high computation time [23]. In 1996, A. Vetuli et al [24] presented Positive Feedback Adiabatic Logic (PFAL), as a new adiabatic logic family, which makes use of a CMOS positive feedback amplifier.…”

Section: Adiabatic Logic Techniquementioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ringcounter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

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Design and analysis of IPAL for ultra low power CRC architecture for applications in IoT based systems

Bhuvana

Bhaaskaran

2019

AEU - International Journal of Electronics and Communications

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Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication

Cited by 15 publications

References 11 publications

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Design and analysis of IPAL for ultra low power CRC architecture for applications in IoT based systems

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