A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Abstract

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a Hardware Description Language (HDL) based modelling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit's invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit Cyclic Redundancy Check (CRC) circuit. The system modelled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems.

Charge Based Power Side-Channel Attack Methodology for an Adiabatic Cipher

“…Charge-recycling adiabatic logic has recently received attention in resourceconstrained applications [22,23]. For example, new charge-recycling logic families have been developed to maximize energy efficiency and increase resistance against power based side-channel attacks [24][25][26].…”