Energy-efficient implementation of AES algorithm on 16nm FPGA

Pandey, Bishwajeet; Bisht, Vaishnavi; Hussain, Dil Muhammad Akbar; Jamil, Mohsin; Hasan, Mohammad Kamrul

doi:10.1109/csnt51715.2021.9509662

Cited by 6 publications

(5 citation statements)

References 8 publications

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“…Decryption: -Upon receiving the ciphertext c, Jack uses his knowledge of the secret key s to recover the original message " III. IMPLEMENTATION OF LATTICE BASED ECC ALGORITHM ON FPGA Field Programmable Gate Arrays (FPGAs) [13,14] represent a class of integrated circuits renowned for their postmanufacturing configurability. Unlike ApplicationSpecific Integrated Circuits (ASICs), which are tailored to specific applications during fabrication, FPGAs offer users the flexibility to define their logic functionality after production.…”

Section: Bmentioning

confidence: 99%

“…It offers compatibility for key lengths of 192, or 256 bits. AES finds widespread usage in securing various applications such as data storage, VPNs, Wi-Fi networks, and secure communication protocols [13,14]. General Applications: AES is extensively used in numerous applications, including securing data at rest, VPNs, Wi-Fi networks, and secure communication protocols.…”

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confidence: 99%

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Implementation of lattice based Cryptograpy cyber forensic system

Kumari,

Anand,

Sharma

et al. 2024

Preprint

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Lattice-based cryptography has emerged as a robust and promising framework for ensuring the security and resilience of cryptographic systems in the face of quantum computing threats. This research paper explores the recent advancements in lattice-based cryptographic techniques, delving into their mathematical foundations, practical implementations, and their significance in the contemporary landscape of information security. The paper provides an in-depth analysis of latticebased cryptographic protocols, including encryption schemes, digital signatures, and key exchange mechanisms. Emphasizing the post-quantum safety and impenetrability of latticebased cryptography, the research investigates the theoretical underpinnings of lattice problems and their computational complexity.

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Section: Bmentioning

confidence: 99%

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confidence: 99%

Implementation of lattice based Cryptograpy cyber forensic system

Kumari,

Anand,

Sharma

et al. 2024

Preprint

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“…Their work shows an achievement of up to 95.29% power saving in comparative study of different I/O standards. Pandey et al (2021b) worked on Kintex Ultrascale+ 16 nm and found that POD 12 and HSTL_I_12 was taking minimum power in execution. Around 94% power reduction was achieved in their experiments.…”

Section: Motivationmentioning

confidence: 99%

“…We have compared results at default frequency and 1.6 GHz frequency. The reason for considering 1.6 GHz frequency for our experiments is based on the outcomes of the work of Pandey et al (2020), in which 1.6 GHz is found to produce best results for energy efficient AES 128 algorithm. This article is categorized in six sections.…”

Section: Introductionmentioning

confidence: 99%

“…modeled power efficient random access memory design in this work, and used five different I/O standards to achieve the goal. Their work shows an achievement of up to 95.29% power saving in comparative study of different I/O standards Pandey et al (2021b). worked on Kintex Ultrascale1 16 nm and found that POD 12 and HSTL_I_12 was taking minimum power in execution.…”

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Comparative performance analysis of AES encryption algorithm for various LVCMOS on different FPGAs

Bisht

Pandey

Budhani

2022

WJE

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Purpose Privacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing. Design/methodology/approach This paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz). Findings The comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design. Originality/value The green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.

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