Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing

Abstract

This paper presents the design of an energy efficient Flash analogue-to-digital converter (ADC) with Threshold Inverter Quantiser (TIQ) comparator employing advanced body biasing to compensate for the effects of parameter variability. The proposed calibration scheme is verified against process, voltage, and temperature (PVT) corners as well as random parameter variability (mismatch). Two proof-of-concept ADCs of 4-and 6bit precision are designed and verified in simulations in 28 nm Fully Depleted Silicon on Insulator (FDSOI) technology. The 6-bit converter achieves sampling rate of 3 GS/s, energy efficiency per conversion step below 20 fJ, and precision of 5.2 effective number of bits (ENOB). The proposed ADC architecture is dedicated to high-speed and low-precision applications, such as communication transceivers and data acquisition systems where area and energy efficiency are paramount. Index Terms-Flash analog-to-digital converter (ADC), offset calibration, threshold inverter quantiser (TIQ), body biasing. This paragraph of the first footnote will contain the date on which you submitted your brief for review. This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671578.

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“…The body gain factor, namely the sensitivity of VT over the body voltage variation, is around 90 mV/V, which is much higher than in conventional bulk technology (25 mV/V). The lower VT of flipped-well devices is beneficial for low-voltage operation, whereas VT tuning capabilities can be profitably exploited to compensate for process, voltage, and temperature variations (PVTs) [28][29][30][31]. However, the lack of dedicated thick-copper metal layers in the BEOL, typically available in SiGe BiC-MOS technologies [6,32], makes crucial passive component design and layout arrangements (e.g., signal paths, power supply and ground interconnections, etc.…”