Implementation and Performance Analysis of Low Power 1 GHz 4-Bit Flash ADC Using III–V Tunnel-FET

Maurya, Ashish; Rahi, Pankaj; Koley, Kalyan; Kumar, J.

doi:10.1007/s00034-022-02187-0

Cited by 1 publication

(2 citation statements)

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“…The simulation results demonstrate the functionality of the memristor-based 4-bit flash ADC, which had a delay time of 70 ns and power consumption of 5.84 mw. A detailed comparison of existing flash ADCs [23][24][25][26] and the one proposed in this work is shown in Table 3, showing that the one proposed in this work improves the power efficiency, delay time, and transistor number.…”

Section: New 3-bit Flash Adcmentioning

confidence: 92%

“…Thus, a comprehensive innovative ADC design from the aspects of the process, device, and structure should be proposed to reduce the chip area and power consumption. Researchers have made various efforts in recent years, such as applying 65 nm CMOS technology to design an ADC that only dissipates 15.5 mW when working at 20 GSps with a 1V supply [23], proposing recoil noise suppression technology to decrease the power consumption of comparators [24], using Tunnel Field Effect Transistors (TFET) to reduce the power consumption of ADCs [25], and proposing an ADC with high performance in power-supply voltage, power consumption, and frequency based on a novel Block-Driven Quasi-Floating Gate (BD-QFG) Current Mirror (CM) structure [26].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors

Dai,

Du,

Xie

et al. 2023

Electronics

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Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.

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Section: New 3-bit Flash Adcmentioning

confidence: 92%