Energy-Efficient Architecture for DP Local Sequence Alignment: Exploiting ILP and DLP

An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification

“…It is seen that the proposed methodology is 1.68-2109.93× and 1.28-8396.78× more energy and resource efficient, respectively. As the methods presented in [12], [41], [42] are sequence alignments, a fair comparison is not maintained while PCpJ and PCpsWD metrics are used on the test data given in Table 6. In the next sub-section, these methods are compared with the proposed methodology using the metrics given in their respective articles.…”

“…In the comparison of our methodology with the hardware methods proposed by Benkrid, Cruz and Neves [12], [41], [42], many of the reads are filtered out by the filtering stage in our design. The earlier defined metrics and performance results in Table 6 take this into account.…”

“…Due to the high cost and energy consumption of GPU based clusters, FPGAs are often preferred for processing genomic data as they offer massive parallelism, low cost and high energy efficiency [12], [14], [18], [20]. Various algorithms for applications like pairwise sequence alignment, database searching, string matching, multiple sequence alignment, read mapping, etc., are designed using reconfigurable FPGA hardware [12], [18]- [20], [24], [41]- [44]. An extensive survey for sequence alignment using reconfigurable platforms is presented in [45].…”