Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor

Tang, Song-Nien; Jan, Fu-Chiang

doi:10.1109/tvlsi.2019.2894751

Cited by 7 publications

(3 citation statements)

References 42 publications

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“…A novel method for the urinary bladder non-invasively volume measuring based on the electrical impedance tomography principles and implemented on FPGA is presented in [25]. The authors [45] designed a novel OCT imaging portable processor implemented on energy-efficient and calibrationaware FPGA. ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture.…”

Section: B Hardware Accelerators For Medical Image Processingmentioning

confidence: 99%

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

et al. 2022

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Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (fieldprogrammable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.INDEX TERMS Medical image processing, discrete wavelet transform, scaled filter coefficients, residue number system, high-performance computing, hardware accelerator, field-programmable gate arrays.

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Section: B Hardware Accelerators For Medical Image Processingmentioning

confidence: 99%

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

et al. 2022

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“…15 Multiplication procedure is the most advanced process in huge power computing applications. 16 Moreover, the multiplication function 17 required more processing time also the framework for such multiplication units are complex. 18 The floating point operation is in the form of sign exponent and mantissa; for the 64 bit floating point multiplication, the bit allocated for sign is one, 11 bit for exponent, and 53 bit for mantissa calculation.…”

Section: Introductionmentioning

confidence: 99%

The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model

Srikanth

Kumar

Ravindra³

et al. 2020

Trans Emerging Tel Tech

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The multiplication strategy is a trending technology in chip programming model; also, it is used in different applications for different purpose. This research aims to develop the floating point double precision Furer Toom cook fast integer multiplication model in the Advanced Encryption Standard process round to enhance the security. In addition, the cryptography algorithms have been broken due to some harmful attack. So the main focus of this present research is to enhance the security measures in communication channel. Moreover, the proposed model is implemented in Xilinx and simulated in cadence 90 nm technology. By comparing the proposed work with recent existing models, the proposed research has reduced the power consumption as 5331.73 nW, thus 89% of power is reduced by the proposed Furer Toom cook multiplication model. The reduction of power enhanced the performance of multiplication algorithm so, while it is utilized in any application, it could not cause any loss of process. In addition, the developed strategy is process within 563 MHz frequency and utilized 11 250 cells. Thus, the proposed model provides better security for all wireless appliances.

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“…

Discrete Fourier Transform (DFT) plays a vital role digital signal processing [1]. Fast Fourier Transform (FFT) is a fast algorithm of DFT, which is widely used in communication [2,3], image processing [4,5], composite material science [6], signal processing [7][8][9], and other fields. DFT has a very high computational complexity ( O N 2 ), so it is difficult to implement on Very Large-Scale Integration (VLSI).

…”

mentioning

confidence: 99%

High performance and resource efficient FFT processor based on CORDIC algorithm

Zhao

Liu

et al. 2022

EURASIP J. Adv. Signal Process.

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Fast Fourier Transform is widely used in communication and signal processing. I propose an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm. By optimizing the intermediate data processing process and the first stage of pipelining, the architecture improves the system's computing speed and reduces the use of registers. I propose a multiplication scheme based on CORDIC and binary decomposition coding to realize complex number multiplication and constant multiplication and to eliminate the use of a multiplier. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

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Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor

Cited by 7 publications

References 42 publications

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients

The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model

High performance and resource efficient FFT processor based on CORDIC algorithm

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