Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices

Jayakumar, Hrishikesh; Raha, Arnab; Raghunathan, Vijay

doi:10.1109/vlsid.2016.52

Cited by 30 publications

(13 citation statements)

References 8 publications

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“…Bhatti and Mottola [29] improved this proposition by distinguishing RAM regions (stack, heap, etc.) and other [30], [31] proposed further improvements. These works define incremental checkpointing.…”

Section: B Checkpointing Mechanismsmentioning

confidence: 98%

MPU-based incremental checkpointing for transiently-powered systems

Berthou

Marquet

Risset

et al. 2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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Transiently-powered devices are a class of small devices powered by energy harvesting. Because such devices are subject to frequent power outages, many recent works propose to checkpoint data residing in volatile RAM into non-volatile RAM. In this article, we propose a new incremental checkpointing mechanism supported by a common hardware component, namely a Memory Protection Unit (MPU). This mechanism leverages the hardware interrupts of the MPU: volatile RAM is read-only on boot and is progressively unlocked as soon as protection violations occur. The MPU interrupt handler is designed to flag the corresponding volatile RAM blocks as dirty, i.e., modified. When a power outage is foreseen to be imminent, the software simply has to copy the dirty blocks from volatile RAM into the non-volatile RAM to ensure application progress over power outages. We validate our approach analytically and in cycle-accurate simulation, and we show that the proposed solution can be easily implemented on real hardware.

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Section: B Checkpointing Mechanismsmentioning

confidence: 98%

MPU-based incremental checkpointing for transiently-powered systems

Berthou

Marquet

Risset

et al. 2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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“…The circles show the latest snapshot before power is lost; any computation after the latest snapshot is a waste of resources. Note that some task-based or static approaches may mitigate wasted computation after a checkpoint by measuring stored energy and comparing it to predictions [21] or observations [41] of the energy required to reach the next task-boundary or checkpoint.…”

Section: (C) Taxonomymentioning

confidence: 99%

Energy-driven computing

Sliper

Cetinkaya

Weddell

et al. 2019

Phil. Trans. R. Soc. A.

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For decades, the design of untethered devices has been focused on delivering a fixed quality of service with minimum power consumption, to enable battery-powered devices with reasonably long deployment lifetime. However, to realize the promised tens of billions of connected devices in the Internet of Things, computers must operate autonomously and harvest ambient energy to avoid the cost and maintenance requirements imposed by mains- or battery-powered operation. But harvested power typically fluctuates, often unpredictably, and with large temporal and spatial variability. Energy-driven computers are designed to treat energy-availability as a first-class citizen, in order to gracefully adapt to the dynamics of energy harvesting. They may sleep through periods of no energy, endure periods of scarce energy, and capitalize on periods of ample energy. In this paper, we describe the promise and limitations of energy-driven computing, with an emphasis on intermittent operation. This article is part of the theme issue ‘Harmonizing energy-autonomous computing and intelligence’.

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“…The circles show the latest snapshot before power is lost; any computation after the latest snapshot is a waste of resources. Note that some task-based or static approaches may avoid wasted computation after a checkpoint by measuring stored energy and comparing it to predictions [7] or observations [12] of the energy required to reach the next task-boundary or checkpoint.…”

Section: Taxonomy Of Existing Ic Strategiesmentioning

confidence: 99%

“…Task-based IC [8,12,16] is a recent development of static IC where the application is divided into a set of tasks that are executed atomically by a runtime. The task division is motivated by protecting static IC against idempotency violations by carefully controlling each task's accesses to nonvolatile memory, thus making code re-execution safe [8].…”

Section: Task-based Static Icmentioning

confidence: 99%

Enabling intermittent computing on high-performance out-of-order processors

Sliper

Balsamo

Weddell

et al. 2018

Proceedings of the 6th International Workshop on Energy Harvesting &Amp; Energy-Neutral Sensing Systems

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Intermittent computing is a new paradigm enabling battery-less computing devices to be powered directly from energy harvesting, enabling IoT devices that are free from the cost, size and lifetime constraints of batteries. To cope with frequent power interruptions, intermittent computing systems save computational progress before power is lost, and restore it when power returns. Recent research in power-neutral operation of multiprocessor system-onchips (MPSoCs), where performance scaling is used to instantaneously match power consumption with supply, motivates the need for intermittent computing on high-performance systems. Existing works provide solutions for microcontrollers, but with the increased complexity of high-performance SoCs, new challenges such as hierarchical memory and dependence on large existing libraries emerge. In this paper, we provide a taxonomy of published intermittent computing methods and identify the most suitable method for high-performance SoCs. The chosen method is then implemented and experimentally validated on an Arm A9 out-of-order application processor. Results show that state can be saved/restored correctly in 8.6 ms for a minimal bare-metal application, which is an order of magnitude faster than the platform's hardware boot time. CCS CONCEPTS • Computer systems organization → Embedded systems; Embedded software; System on a chip;

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Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices

Cited by 30 publications

References 8 publications

MPU-based incremental checkpointing for transiently-powered systems

MPU-based incremental checkpointing for transiently-powered systems

Energy-driven computing

Enabling intermittent computing on high-performance out-of-order processors

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