End-to-end validation of architectural power models

Abstract

While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper, we examine the accuracy of commonly used architectural power models using the TRIPS system as a case study. We use the TRIPS processor because we have ready access to the TRIPS architectural simulators, RTL simulators, and hardware. Access to all three levels of the design provides key insights that are missing from previously published power validation studies. First, we show that applying common architectural power models out-of-the-box to TRIPS results in an underestimate of the total power by 65%. Next, using a detailed breakdown of an accurate RTL power model (6% average error), we identify and quantify the major sources of inaccuracies in the architectural power model. Finally, we show how fixing these sources of errors decreases the inaccuracy to 24%. While further reductions are difficult due to systematic modeling errors in the simulator, we conclude with recommendations on where to focus attention when building architectural power models.

Processor power estimation techniques: a survey

“…Most of the time, researchers try to apply standard scaling rules to get the power dissipation values for a target technology. However, (Govindan et al, 2009) establish that scaling methodologies underestimate the latch capacitance by up to 40%. As the design methodology evolves, the original assumptions regarding the design of a certain functional unit cease to hold.…”

Quantifying sources of error in McPAT and potential impacts on architectural studies

“…Control logic and arithmetic logic. These are known to be difficult to model, especially at the architectural level [16,31]. Since the vast majority of McPAT's modeled structures are caches, array-based structures and CAMs, the subset area is merely 25-50% of the total area of the IFU, ISU, and LSU, as shown by instruction decoder, and aspects of instruction issue selection.…”

“…Govindan et al [16] validated a Wattch power model for a prototype TRIPS processor [7] against RTL simulations and hardware measurements to categorize and quantify the types of modeling error observed. We distinguish our work from theirs because POWER7 is a commercial superscalar server multicore chip whose design is much more complex than the TRIPS prototype, so it can potentially reveal edge cases in power models that a simpler CPU would not.…”

“…Fine-grained validation requires access to detailed design data often not available in academia, and one notable example of such validation is work by Govindan et al for the TRIPS microarchitecture [16]. In this work, we rigorously assess McPAT's area and dynamic power models for the cores of a conventional general-purpose microprocessor, the IBM R POWER7 TM server multicore chip.…”