Encapsulating Application Subsystems Using the DECOS Core OS

Schlager, Martin; Herzner, Wolfgang; Wolf, Andreas; Gründonner, Oliver; Rosenblattl, Maximilian; Erkinger, Erwin

doi:10.1007/11875567_29

Cited by 10 publications

(4 citation statements)

References 1 publication

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“…We select n= [6,10], m= [2,4,6,8], 𝛼= [7,20], u=[0.1 to 1.0 step=0.05], R max = [1,2,3,4], and R=[3,4, … ,12, … ,16] and generate a total of 1.28x10 6 task sets and allocates these task sets using SRTA, SPA, ROP, and FFD. The results presented in Figure 10 show that the SRTA performance is comparable on multiple processor configurations, eg, on two, four, six, and eight processors (cores).…”

Section: Resultsmentioning

confidence: 99%

“…In the real‐time partitioned scheduling, the tasks are allocated statically on all processors with scheduler running on each processor independently, and the migration of statically allocated tasks to the other processors is not permitted. There are many Real‐Time Operating Systems (RTOS) that support partitioned scheduling, eg, Tresos, 6 LynxOS, 7 DECOS, 8 and VxWorks 9 . The uniprocessor fixed priority Rate Monotonic Scheduling (RMS), 10 dynamic priority Earlier Deadline First (EDF), 10 and dynamic priority Deadline Monotonic (DM) 11 schemes can be used in partitioned scheduling, eg, Partitioned‐RMS, Partitioned‐EDF, and partitioned‐DM scheduling.…”

Section: Introductionmentioning

confidence: 99%

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Real‐time partitioned scheduling: Exploiting the inter‐resource affinity for task allocation on multiprocessors

Akram

Bai

et al. 2019

Concurrency and Computation

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Real-time edge computing is forging its place in cloud computing rapidly, and requirements for high-performance edge devices are becoming increasingly complex. Multiprocessor edge devices are an attractive choice to meet these higher performance requirements. However, multiprocessor devices encounter inherent challenges when handling on-chip shared resources. The concurrent access to these resources by the tasks requesting more than one shared resource and running on multiple processors may face huge blocking times, which can lead to missed hard real-time deadlines and cause a catastrophic system failure. To reduce the task blocking time, we propose a task allocation algorithm that takes advantage of inter-resource affinity and allocates all the tasks accessing multiple shared resources having inter-resource affinity on the same processor of the multiprocessor. The proposed algorithm reduces global resources and remote blocking, which subsequently increase schedulability of task sets and reduce the processor utilization. In our experiments, we compare the proposed task allocation algorithm SRTA with existing well-known task allocation strategies SPA, ROP, and blocking-agnostic FFD. The experimental results reveal that the SRTA, on the average, can allocate 1.80, 2.34, and 3.14 times more task sets as compared to ROP, SPA, and FFD, respectively and reduces the number of globally shared resources significantly.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Real‐time partitioned scheduling: Exploiting the inter‐resource affinity for task allocation on multiprocessors

Akram

Bai

et al. 2019

Concurrency and Computation

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“…The allocation of computational resources (e. g., memory, CPU time) to jobs occurs using a partitioning operating system with support for fault isolation and modular certification [21,22]. The partitioning operating system implements mechanisms for spatial and temporal partitioning in order to encapsulate the individual jobs.…”

Section: Node Computersmentioning

confidence: 99%

A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture

Schlager

Obermaisser

Elmenreich

2007

Software Technologies for Embedded and Ubiquitous Systems

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Abstract. In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as recently developed in DE-COS (Dependable Embedded COmponents and Systems), an integrated project within the Sixth Framework Programme of the European Commission. Focusing on the interconnection between the simulated environment and the Integrated System Under Test (ISUT), our approach involves the concept of a Smart Virtual Transducer (SVT) that replaces the physical transducers of the ISUT without a probe effect on the ISUT. Our approach enables a complexity reduction for setting up an HiL simulation and supports a well-designed scalable interface to an integrated architecture. Furthermore, we support non-intrusive, deterministic interaction between the environment simulation system and the ISUT in order to guarantee reproducible test-runs. We show an exemplary application of the proposed concept by tailoring the generic components of the proposed simulation approach to an automotive park assistant system.

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“…Temporal and spatial partitioning between applications is ensured by encapsulated execution environments (in nodes) [4] and virtual networks (communication bus) [5]. The foundation for the DECOS technology is a time-triggered core architecture which has to provide services such as predictable message transport and fault-tolerant clock synchronization.…”

Section: Introductionmentioning

confidence: 99%

Towards a DECOS Fault Injection Platform for Time-Triggered Systems

Eriksson

Vinter

Leiner

et al. 2007

2007 5th IEEE International Conference on Industrial Informatics

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This paper presents a fault injection platform targeting the communication bus in the DECOS platform, which is using a time-triggered communication protocol such as TTP or FlexRay. Communication errors are injected by a disturbance node, which emulates errors caused by external sources, e.g. from electrical relays in road vehicles or from lightning affecting airplanes. The platform is flexible and the communication protocol can be reconfigured from TTP to FlexRay or vice versa. The experiments are configured by XML scripts and controlled by Lauterbach TRACE32 software and hardware. Raw data from the experiments are stored in SRAM memory without halting the program execution so only minor time intrusiveness is introduced for logging data. After each experiment raw data are downloaded from memory, automatically parsed and converted into integer and e.g. float data types, and finally stored in a MySQL database for analysis. Several analysis functions are developed to evaluate the effectiveness of hardwareimplemented and software-implemented error detection and recovery mechanisms.

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Encapsulating Application Subsystems Using the DECOS Core OS

Cited by 10 publications

References 1 publication

Real‐time partitioned scheduling: Exploiting the inter‐resource affinity for task allocation on multiprocessors

Real‐time partitioned scheduling: Exploiting the inter‐resource affinity for task allocation on multiprocessors

A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture

Towards a DECOS Fault Injection Platform for Time-Triggered Systems

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