Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!

Ryckaert, Julien; Baert, Rogier; Verkest, D.; Na, M. H.; Weckx, Pieter; Jang, Doyoung; Schuddinck, P.; Chehab, Bilal; Patli, S.; Sarkar, Santonu; Zografos, Odysseas

doi:10.1109/iedm19573.2019.8993631

Cited by 48 publications

(29 citation statements)

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“…The main difference is that additional dielectric wall preparation technology is required, as shown in Fig. 19 [104] . Compared with conventional stacked nanosheets, dielectric wall isolation has the following advantages: (1) physically isolated n-type metal-oxidesemiconductor (NMOS) and PMOS gate structures can simplify metal gate modules, and (2) the risk of shortcircuiting NMOS and PMOS source and drain while epitaxy is avoided.…”

Section: Forksheet Devicesmentioning

confidence: 99%

“…Channel material/direction L g (nm) D Fig. 19 Dielectric wall and metal grid module technology in forksheet devices [104] .…”

Section: Forksheet Devicesmentioning

confidence: 99%

“…Dan Zhang et al: Advanced Process and Electron Device Technology 549 standard cell templates are shown in Fig. 20 [104] . The proposal of the complementary FET (CFET) structure provides a choice in the vertical direction for reducing the standard cell area.…”

Section: Forksheet Devicesmentioning

confidence: 99%

“…NMOS devices are generally "folded" on PMOS devices; that is, transistors with different conductivity types are stacked three-dimensionally, which eliminates the bottleneck of n-to-p separation. Thus, the standard cell area is greatly reduced [104] , as shown in Fig. 21.…”

Section: Forksheet Devicesmentioning

confidence: 99%

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Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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This article reviews advanced process and electron device technology of integrated circuits, including recent featuring progress and potential solutions for future development. In 5 years, for pushing the performance of fin field-effect transistors (FinFET) to its limitations, several processes and device boosters are provided. Then, the three-dimensional (3D) integration schemes with alternative materials and device architectures will pave paths for future technology evolution. Finally, it could be concluded that Moore's law will undoubtedly continue in the next 15 years.

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Section: Forksheet Devicesmentioning

confidence: 99%

“…Channel material/direction L g (nm) D Fig. 19 Dielectric wall and metal grid module technology in forksheet devices [104] .…”

Section: Forksheet Devicesmentioning

confidence: 99%

Section: Forksheet Devicesmentioning

confidence: 99%

Section: Forksheet Devicesmentioning

confidence: 99%

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Advanced process and electron device technology

Zhang¹,

Su²,

Chang³

et al. 2022

Tsinghua Sci. Technol.

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“…Our NS3K standard cells use 5 tracks for cell height. Previous studies discuss issues that occur when power is supplied in 5 (or less) track cells [16], [17]. One breakthrough for the power supply problem in these cells is the Buried Power Rail (BPR) [4], [5], [13].…”

Section: A Buried Power Railmentioning

confidence: 99%

NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes

Kim

Jeong

Woo

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.

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