Enabling sizing for enhancing the static noise margins

Beiu, Valeriu; Beg, Azam; Ibrahim, Walid; Kharbash, Fekri; Alioto, Massimo

doi:10.1109/isqed.2013.6523623

Cited by 15 publications

(15 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Additionally, L of all transistors should be increased slightly over L min , allowing to maintain positive SNM's when scaling into subthreshold. Still, ULV CMOS circuits present large imbalances between nMOS and pMOS transistors [5], [9], [10], reducing their SNM's [12], [13]. Calhoun et al [12] argued that different sizings are needed for above and sub-threshold, a claim also supported by Blesken et al [13], both papers pointing to the need to design specifically for sub-threshold, as gate sizing for nominal V DD are not Pareto optimal in subthreshold [13].…”

Section: Upsizing Length (Unconventional Sizing)mentioning

confidence: 99%

“…For CMOS gates a transistor sizing method which aims to maximize SNM's has been presented in [5]. For understanding it, we start from the switching probability of a transistor [18]:…”

Section: Maximizing the Static Noise Marginsmentioning

confidence: 99%

“…This gives the SNM optimum channel length (L opt ). Exact calculations for 22nm (PTM HP v2.1), give L opt_nMOS = 25.3nm, and L opt_pMOS = 29.8nm, which are just 0.4nm larger than those estimated in [5]. We shall call this the 2L-OPT sizing method as requiring two different values for L. Sizing in very small increments can be envisaged using optical proximity correction [8], [19].…”

Section: Maximizing the Static Noise Marginsmentioning

confidence: 99%

“…We shall call this method 1L-VBS (one L opt using V bs ). This is differnt from [5] where nMOS and pMOS transistors require different L opt , hence the name 2L-OPT (two L opt ). We will show that CMOS gates sized using 1L-VBS have SNM's very close to gates sized using 2L-OPT while being faster and having lower power and energy consumption.…”

Section: Introductionmentioning

confidence: 97%

“…This paper improves on a transistor sizing method which aims to maximize the SNM's of CMOS gates by slightly increasing the channel length (L) and balancing the voltage transfer characteristics (VTCs) [5]. The enhancements are: (i) the exact calculation of the threshold voltage (V th ), which leads to precise L's; (ii) more accurate estimations of SNMs by using the maximum square method; and (iii) relying on biasing (V bs ) for achieving the same L opt for all transistors.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Kharbash

Beiu

Tache

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

View full text Add to dashboard Cite

This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (V th ) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (V bs ) for having a single L opt for all transistors (as opposed to having two different L opt , one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although V th and L change by ~10%, by using V bs we can still achieve very high SNM's, while additionally reducing power and energy to ~50%.

show abstract

Section: Upsizing Length (Unconventional Sizing)mentioning

confidence: 99%

“…For CMOS gates a transistor sizing method which aims to maximize SNM's has been presented in [5]. For understanding it, we start from the switching probability of a transistor [18]:…”

Section: Maximizing the Static Noise Marginsmentioning

confidence: 99%

Section: Maximizing the Static Noise Marginsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Kharbash

Beiu

Tache

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

View full text Add to dashboard Cite

show abstract

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

Beg

2014

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.

show abstract