Enabling quality-of-service in nanophotonic network-on-chip

Ouyang, Ouyang; Xie, Weibo

doi:10.1109/aspdac.2011.5722212

Cited by 9 publications

(4 citation statements)

References 15 publications

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“…In [37], frame-based arbitration is used to provide QoS, in terms of differentiated bandwidth allocation, for an architecture similar to Corona. The so-called FlexiShare architecture presented in [38] can be viewed as a combination of Firefly and Corona.…”

Section: Related Workmentioning

confidence: 99%

A Fair Admission Control Mechanism for Efficient Utilization of Resources in On-chip Nanophotonic Crossbars

Mirsadeghi¹,

Khonsari²,

Talebi³

et al. 2015

Preprint

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Advances in CMOS-compatible photonic elements have made it plausible to exploit nanophotonic communications to overcome the limitations of traditional NoCs. Amongst various proposed nanophotonic architectures, optical crossbars have been shown to provide high performance in terms of bandwidth and latency.In general, optical crossbars provide a vast volume of network resources that are shared among all the cores within the chip. In this paper, we present a fair and efficient admission control mechanism for shared wavelengths and buffer space in optical crossbars. We model buffer management and wavelength assignment as a utility-based convex optimization problem, whose solution determines the admission control policy. Thanks to efficient convex optimization techniques, we obtain the globally optimal solution of the admission control optimization problem by using simple and yet efficient iterative algorithms. We cast our solution procedure as an iterative algorithm to be implemented a central admission controller. Our experimental results corroborate the gain that can be obtained by using such an admission controller to manage the shared resources of the system. Furthermore, they confirm that the proposed admission control algorithm works well for various traffic patterns and parameters, and evinces a tractable scalability with increase in the number of cores of the crossbar.

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Section: Related Workmentioning

confidence: 99%

A Fair Admission Control Mechanism for Efficient Utilization of Resources in On-chip Nanophotonic Crossbars

Mirsadeghi¹,

Khonsari²,

Talebi³

et al. 2015

Preprint

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“…5: The ultimate future computer system architecture with a combination of three disruptive future memory and interconnect technologies: emerging NVM, 3D integration, and on-chip/off-chip optical interconnects. features such as low power and high bandwidth [25], [26], there are also key challenges needed to be addressed to providing robust and reliable on-chip communication. Among many challenges, the thermal sensitivity and process variations (PV) of silicon photonic devices are the key issues [27].…”

Section: Pcram/reram Memory Tsvsmentioning

confidence: 99%

Future Memory and Interconnect Technologies

Xie¹

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

Self Cite

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The improvement of the computer system performance is constrained by the well-known memory wall and power wall. It has been recognized that the memory architecture and the interconnect architecture are becoming the overwhelming bottleneck in computer performance. Disruptive technologies, such as emerging non-volatile memory (NVM) technologies, 3D integration, and optical interconnects, are envisioned as promising future memory and interconnect technologies that can fundamentally change the landscape of the future computer architecture design with profound impact. This invited survey paper gives a brief introduction of these future memory and interconnect technologies, discusses the opportunities and challenges of these new technologies for future computer system designs.

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“…[4] proposed fair token channel and fair token slot mechanisms for starvation avoidance. Quality-of-service (QoS) support for MWSR nanophotonic NoC is studied in [6] and [3].…”

Section: B Network Topologies For Onocmentioning

confidence: 99%

RCBus: Row-Column Bus Topology for Optical Network-on-Chip

Chen

2012

ElAEE

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Abstract-Future chip multi-processors (CMPs) will require high-performance yet low-energy networks-on-chip to provide scalable communication for the increasing number of cores. CMOS-compatible nanophotonic interconnects have recently emerged as a promising candidate for replacing traditional electrical network-on-chip, by providing high bandwidth chipwide communication at low latency and power. In this paper, we utilize the emerging nanophotonic technology and propose RCBus, an optical network-on-chip topology in which multiple nanophotonic buses are uniformly distributed in each row and column of a two-dimensional torus network. Each bus employs a dense-wavelength-division-multiplexing optical waveguide to enable high-bandwidth express traversal along each dimension. We use multiple write single-read schemes and virtual channel based token protocol to implement light-speed arbitration and flow control. The optical-electrical interface is also studied in the paper. The proposed optical network-on-chip can exploit the advantages of both photonic bus and direct torus topology. Simulation results under synthetic and real-world application traffic show that RCBus is 2X better in terms of performance than the electrical mesh network-on-chip while saving nearly 30% power, and achieves on average 24 % throughput improvement at much lower cost compared to the state-of-theart optical network.

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Enabling quality-of-service in nanophotonic network-on-chip

Cited by 9 publications

References 15 publications

A Fair Admission Control Mechanism for Efficient Utilization of Resources in On-chip Nanophotonic Crossbars

A Fair Admission Control Mechanism for Efficient Utilization of Resources in On-chip Nanophotonic Crossbars

Future Memory and Interconnect Technologies

RCBus: Row-Column Bus Topology for Optical Network-on-Chip

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