2020
DOI: 10.1039/d0qi00038h
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Enabling high performance n-type metal oxide semiconductors at low temperatures for thin film transistors

Abstract: The review highlights low temperature activation processes for high performance n-type metal oxide semiconductors for TFTs.

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Cited by 45 publications
(21 citation statements)
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“…give breakdowns of the various approaches for low temperature fabrication of MOs. [ 135,136 ] Among those approaches, the variation in precursor chemistry has proven quite effective. Here, the work by Cochran et al.…”
Section: Flexible Electronic Devicesmentioning
confidence: 99%
“…give breakdowns of the various approaches for low temperature fabrication of MOs. [ 135,136 ] Among those approaches, the variation in precursor chemistry has proven quite effective. Here, the work by Cochran et al.…”
Section: Flexible Electronic Devicesmentioning
confidence: 99%
“…In order to develop PDs through low cost and low temperature fabrication processes with good operation stability in air, solution-processed metal oxide (M-O) based photoactive thin films synthesized from metal precursors by sol-gel chemistry are considered. Conventionally, high temperature thermal annealing processes are usually needed for promoting the condensation reaction for forming crosslinked M-O network, [29] it is essential to develop technics to lower down the thermal budget [30] of functional sol-gel M-O film on resin based substrates. So far, low temperature annealing processes including the adoption of deep-ultraviolet (DUV) light for activating photochemical reaction [31][32][33][34][35] or light absorber doping for efficiently extracting heat during NIR laser irradiation [36] has been proposed to realize low temperature sol-gel M-O film curing.…”
Section: Doi: 101002/admt202201026mentioning
confidence: 99%
“…From these technical backgrounds, the introduction of AOS channel thin film transistor (TFT) has been pursued to reduce the cell footprint and open the possibility of stacking individual cells. For developing and characterizing the devices with nanoscale AOS channels, the device feasibility should be urgently explored for potential implementation of highly scaled devices in future logic and memory applications. There have been several approaches to implement short-channel oxide TFTs, such as 3D vertical or self-aligned coplanar structures. Alternatively, during the progress of device scaling for the AOS TFTs, short-channel effects (SCEs) of the fabricated devices should be fairly evaluated. , Particularly, the gate-stack formation conditions and process steps are major concerns to be carefully designed.…”
Section: Introductionmentioning
confidence: 99%