Emulating Mammalian Vision on Reconfigurable Hardware

Kestur, Srinidhi; Park, Mi Sun; Sabarad, J.; Dantara, Dharav; Narayanan, Vijaykrishnan; Yang, Chen; Khosla, Deepak

doi:10.1109/fccm.2012.33

Cited by 24 publications

(17 citation statements)

References 13 publications

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“…Much work has already been completed on the design of dedicated hardware for acceleration of MLPs [18]- [23] or other types of NNs, be they Convolutional Neural Networks [5]- [9], Deep Belief Networks [10]- [12], Hierarchical Model and X [13], or more biologically accurate models [14]- [17]. We, however, propose what we believe is the first instance of an NN accelerator architecture that supports the simultaneous execution of multiple NNs.…”

Section: B Neural Network Acceleratorsmentioning

confidence: 99%

“…1) Specialized hardware architectures that improve the performance and energy efficiency of machine learning techniques [5]- [17] 2) Schemes for extending the exploitation of NN processing to applications that are not explicitly programmed to use them, e.g., approximate computing [18]- [23] or auto-parallelization [24] These diverse implementations and usage cases drive fascinating innovation. As diversity increases, however, a gap is developing between these innovations and the state of today's hardware and software.…”

Section: Introductionmentioning

confidence: 99%

“…Such an interface allows NN hardware diversity to expand while, at the same time, encouraging a diverse set of software use cases to be explored. From a hardware perspective, one would like to see the continued exploration of the full spectrum of NN accelerator technologies from dedicated NN digital logic units [5]- [13], [18]- [23] to biologically inspired analog/sub-threshold implementations [14]- [17]. Similarly, from a software perspective, one wants to encourage both explicit and implicit usage models to grow.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Towards General-Purpose Neural Network Computing

Eldridge¹,

Waterland

Seltzer³

et al. 2015

2015 International Conference on Parallel Architecture and Compilation (PACT)

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Abstract-Machine learning is becoming pervasive; decades of research in neural network computation is now being leveraged to learn patterns in data and perform computations that are difficult to express using standard programming approaches. Recent work has demonstrated that custom hardware accelerators for neural network processing can outperform software implementations in both performance and power consumption. However, there is neither an agreed-upon interface to neural network accelerators nor a consensus on neural network hardware implementations. We present a generic set of software/hardware extensions, X-FILES, that allow for the generalpurpose integration of feedforward and feedback neural network computation in applications. The interface is independent of the network type, configuration, and implementation. Using these proposed extensions, we demonstrate and evaluate an example dynamically allocated, multi-context neural network accelerator architecture, DANA. We show that the combination of X-FILES and our hardware prototype, DANA, enables generic support and increased throughput for neural-networkbased computation in multi-threaded scenarios. These diverse implementations and usage cases drive fascinating innovation. As diversity increases, however, a gap is developing between these innovations and the state of today's hardware and software. I. INTRODUCTION1 As such it is worth con-

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Section: B Neural Network Acceleratorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Towards General-Purpose Neural Network Computing

Eldridge¹,

Waterland

Seltzer³

et al. 2015

2015 International Conference on Parallel Architecture and Compilation (PACT)

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“…Regardless of the massively parallel architecture, constructing a saliency map is a computationally heavy task. The best reported times on CPU-based implementations are of an order of~50 ms for a single map [19], the time which doubles for a stereo system, after which some highlevel visual processing is done in the later stages in the visual processing pipeline. This limits the applicability of the classical saliency map approach for fast real-world robotic problems such as real-time adaptation to perturbations in grasping tasks with obstacle avoidance.…”

Section: Current Shortcomings Of Attention-based Models For Robot mentioning

confidence: 99%

Modulating vision with motor plans: A biologically-inspired efficient allocation of visual resources

Lukic

Billard

Santos-Victor³

2013

2013 13th IEEE-RAS International Conference on Humanoid Robots (Humanoids)

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Abstract-This paper presents a novel, biologically-inspired, approach for an efficient management of computational resources for visual processing. In particular, we modulate a visual "attentional landscape" with the motor plans of a robot. The attentional landscape is a more recent, general and a more complex concept of an arrangement of spatial attention than a simple ''attentional spotlight" or a ''zoom-lens" model of attention. A higher attention priority for visual processing must be given to manipulation-relevant parts of the visual field, in contrast with other, manipulation-irrelevant, parts. Hence, in our model visual attention is not exclusively defined in terms of visual saliency in color, texture or intensity cues, it is rather modulated by motor (manipulation) programs. This computational model is supported by recent experimental findings in visual neuroscience and physiology. We show how this approach can be used to efficiently distribute limited computational resources devoted to visual processing, which is very often the computational bottleneck in a robot system. The model offers a view on the well-know concept of visual saliency that has not been tackled so far, thus this approach can offer interesting alternative prospects not only for robotics, but also for computer vision, physiology and neuroscience. The proposed model is validated in a series of experiments conducted with the iCub robot, both using the simulator and with the real robot.

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“…For these reasons, it is desirable to improve performance by employing more powerful reconfigurable hardware accelerators. Thus, some proposals focus on developing an FPGA framework for an end-to-end attention and recognition system using saliency and HMAX accelerators [13] [14] [15]. Particular optimisation efforts have been proposed high performance hardware architectures for bottom-up spatio-temporal visual saliency models.…”

Section: Previous Related Workmentioning

confidence: 99%

A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture

Chenini¹

2017

ijacsa

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Abstract-This paper presents an object recognition approach of outdoor autonomous systems identifying the nature of the interested object when observing an image. Therefore, seeking for effective and robust recognition method, the proposed approach is performed using a novel saliency based feature detector/descriptor which is combined with an object classifier to identify the nature of objects in an indoor or an outdoor environment. As known, bottom-up visual attention computational models need a considerable computational power and communication cost. A major challenge in this work is to deal with such image processing applications managing a large amount of the information processing and to work within real-time requirements by improving the processing speed.Based on interesting approach designing specific architectures for parallelism, this paper presents a solution for rapid prototyping of saliency-based object recognition applications. In order to meet computation and communication requirement, the developed pipelined architectures are composed of identical processing modules which can work concurrently with distributed memories and compute in parallel several sequential tasks with a high computational cost. We present hardware implementations with performance results on an Xilinx System-on-Programmable Chip (SoPC) target. The experimental results including execution times and application speedups as well as requirements in terms of computing resources show that the proposed homogeneous network of processors is efficient for embedding the proposed image processing application.

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Emulating Mammalian Vision on Reconfigurable Hardware

Cited by 24 publications

References 13 publications

Towards General-Purpose Neural Network Computing

Towards General-Purpose Neural Network Computing

Modulating vision with motor plans: A biologically-inspired efficient allocation of visual resources

A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture

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