Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Abstract

Present CMOS technology with scaled channel lengths exhibited higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption with increased vulnerability. Additionally, spin transfer torque magnetic tunnel junction (STT-MTJ) and CMOS based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel FET (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET based sense amplifier based logic (SABL) gates have been proposed that achieve 3× lower energy consumption compared to Si FinFET SABL designs. Further, utilizing TFET SABL gates, TFET Pride S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption compared to FinFET designs. With resulted lower static power consumption, TFET SABL based crypto systems can show lower vulnerability to static power side-channel attacks. Besides, proposed STT-MTJ and TFET LiM gates achieves 4× lower energy consumption compared to STT-MTJ and FinFET designs. Moreover, these gates have been explored in logic encryption/locking technique that shows 3.1× lower energy consumption compared to STT-MTJ and FinFET based design. KeywordsTunnel FET (TFET) • Differential power analysis (DPA) • Sense amplifier based logic (SABL) • Spin transfer torque magnetic tunnel junction (STT-MTJ) • Logic-in-memory (LiM) • Logic encryption/locking

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

“…The possible challenges and solutions for these particular drawbacks are shown in Figure .2 [46], [56]. The other side of TFET also has some special characteristics that may make them less vulnerable to specific side-channel attacks, in the work demonstrated with the TFET SABL makes it less susceptible to static power side-channel intrusions [47] and it can be used in the neuromorphic computing like Spiking Neural Networks (SNNs) based on TFET neurons are presented for pattern recognition applications, showcasing its great advantage on energy effectiveness [48]. Still, TFET can be explored to the strong hardware secure designs because of its peculiar characteristics like side-channel attacks counter measures [49], hardware primitives like physical unclonable methodologies [50], true random number generators [51], hardware obfuscations [52] and hardware Trojans [53]- [55].…”

“…So this offers enhanced security coverage across a broader range of threats when contrasted with alternative obfuscation techniques like IC camouflaging and split manufacturing. To mitigate the risk of side-channel attacks, the authors in paper [47] sug-gest the adoption of SABL gates, which have demonstrated superior resistance to Differential Power Analysis (DPA) when compared to traditional CMOS gates. Additionally, the proposed TFET SABL gates further bolster DPA resilience by reducing data dependencies on device power consumption.…”

“…TFET-based SABL gates are suggested to achieve three times lower energy consumption compared to Si FinFET SABL designs. Furthermore, a TFET PRIDE S-box, designed with TFET SABL gates, exhibits higher DPA resilience with 3.2× lower energy consumption compared to FinFET designs[47]. A different design approach shows how TFET-based Current Mode Logic (CML) might enhance DPA robustness and retain minimal power consumption in a targeted design.…”