Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

Bheemana, Renuka Chowdary; Japa, Aditya; Yellampalli, Siva; Vaddi, Ramesh

doi:10.1016/j.mejo.2023.105711

Cited by 8 publications

(4 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The NCFET PRESENT-80 cipher design undergoes evaluation against DPA attacks, and the findings reveal that the NCFET-based cipher design exhibits a significantly higher level of resilience when relative to the baseline CMOS design. It achieves an approximately fourfold increase in the attacker's effort ratio and maintains a low Signal-to-Noise Ratio (SNR) [147], some other side-channel attacks in CNN model [148].…”

Section: H Negative Capacitance Fet(ncfet)mentioning

confidence: 99%

“…The NCFET-based PRESENT-80 block cipher design achieves approximately 3.2× lower energy consumption compared to the baseline 40 nm CMOS design under similar constraints. Evaluation against DPA attacks shows high resilience, with the NCFET-based design achieving around 4× increased attacker effort ratio and low SNR values compared to the baseline CMOS design[147]. RRAM provides opportunities to counteract SCAs/DPAs due to inherent characteristics such as write time variability, ultra-low power (0.1-3 pJ/bit), and high density (4F²).…”

mentioning

confidence: 99%

See 1 more Smart Citation

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

View full text Add to dashboard Cite

To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this convergence poses a significant security challenge, as adversaries can exploit it to extract unauthorized information, compromise system performance, and obtain secret keys. Meanwhile, traditional CMOS features have limitations in addressing hardware vulnerabilities and security threats, so promising post-silicon technologies offer potential solutions. Beyond-CMOS technologies offer avenues to fortify hardware security through distinct physical properties and nontraditional computing paradigms. These advancements bolster authentication processes, enhance key generation mechanisms, ensure hardware integrity and fortify resilience against side-channel attacks, hardware Trojans and quantum-resistant cryptography in securing hardware systems. This article provides a detailed review of hardware security, encompassing the identification and mitigation of threats, the implementation of robust countermeasures, the utilization of innovative primitives, countermeasures, various methodologies and distinct features offered by emerging technologies to resist hardware threats.Moreover, strategies to address challenges, explore future directions, and outline plans for achieving further research outcomes have been put forth in this field.

show abstract

Section: H Negative Capacitance Fet(ncfet)mentioning

confidence: 99%

mentioning

confidence: 99%

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Srinivas,

Elango

2024

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Where V OH and V OL define the maximum output voltage and minimum output voltage when output levels are logic 1 and logic 0, respectively [22], all parameters are tabulated in table 4.…”

Section: Noise Margin Calculationmentioning

confidence: 99%

“…For the launch of ferroelectric HfO 2 -based NCFET, one must demonstrate its ultralow supply voltage usage over the existing Ferroelectric based NCFET. A practical guideline for the device design should be followed to achieve fast-speed operations [20][21][22]. And also, for the process development, material parameters should be properly chosen.…”

Section: Introductionmentioning

confidence: 99%

DFT based atomic modeling and temperature analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET

Mann,

Chaujar

2023

Phys. Scr.

View full text Add to dashboard Cite

In this report, Density Functional Theory (DFT) based calculation using a Quantum Atomistic Tool Kit (ATK) simulator is done for the hafnia-based ferroelectric material. The band structure, projected density of states (PDOS), and Hartree potential (VH) are taken into account for hafnium oxide (HfO2) and silicon-doped hafnium oxide (Si-doped HfO2). Further, we analyze the temperature variation impact on analog parameters and voltage transfer characteristic (VTC) curve of inverter application of Modified Negative Capacitance Field-Effect-Transistor (NCFET) using the Visual Technology-Computer-Aided-Design (TCAD) simulator. The Modified NCFET structure enhances the DC parameters like leakage current (IOFF) and Subthreshold Swing (SS) compared to the conventional NCFET structure. With the temperature impact, the variation in the parameters of Modified NCFET is discussed at 250 K, 275 K, 300 K, 325 K, and 350 K like transconductance (gm), output conductance (gd), early voltage (VEA) shows the increment as we move from 250 K to 350 K. The short channel effects (SCEs) like Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) decrease with the temperature fall at 32.98% and 34.74%, respectively. Further, the VTC curve, Noise Margin (NM), and propagation delay of Modified NCFET-based inverter are discussed with the impact of temperature. The propagation delay for the circuit decreased by 67.94% with the rise in the temperature. These factors show that the Modified NCFET-based inverter gives a fast switching performance at high temperatures.

show abstract

DFT-based Atomic Calculation of Si-doped HfO2 and Effect of its Negative Capacitance on Analog/RF, and VTC Parameters of MOSFET

Mann,

Chaujar

2023

Silicon

View full text Add to dashboard Cite

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

Cited by 8 publications

References 26 publications

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories

DFT based atomic modeling and temperature analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET

DFT-based Atomic Calculation of Si-doped HfO2 and Effect of its Negative Capacitance on Analog/RF, and VTC Parameters of MOSFET

Contact Info

Product

Resources

About