Emerging Steep-Slope Devices and Circuits: Opportunities and Challenges

Li, Xueqing; Kim, Moon Seok; George, Sumitha; Aziz, Ahmedullah; Jerry, Matthew; Shukla, Nikhil; Sampson, John J.; Gupta, Sumeet Kumar; Datta, Suman; Narayanan, Vijaykrishnan

doi:10.1007/978-3-319-90385-9_6

Cited by 9 publications

(4 citation statements)

References 78 publications

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“…The internal voltage boosting effect due to the charge density mismatch between the ferroelectric (FE) and dielectric (DE) thin DOI: 10.1002/adfm.202304754 films (or semiconductor channel) has been suggested as a feasible method to improve the field effect transistor (FET) performance further by decreasing the subthreshold slope (SS) of the transfer curve (drain current-gate voltage [I D -V G ] property). [1][2][3][4][5][6] Such a specific FET has been regarded as the negative capacitance FET (NCFET), where the surface potential modulation of the semiconductor channel could be even higher than the gate voltage variation. Moreover, the NCFET is unique in that it may not sacrifice other device performance, such as high saturation drive current and low off leakage current, which have hardly been achieved by other candidates, such as tunneling FET and cold-source FET.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the NCFET is unique in that it may not sacrifice other device performance, such as high saturation drive current and low off leakage current, which have hardly been achieved by other candidates, such as tunneling FET and cold-source FET. [6,7] However, the practical implementation of NCFET has been deterred by several non-idealities. The most significant nonideality might be the involvement of hysteresis in the transfer curve, possibly due to the hysteretic FE switching of the FE layer integrated into the gate stack.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Exploring the Physical Origin of the Negative Capacitance Effect in a Metal–Ferroelectric–Metal–Dielectric Structure

Park,

Byun,

Kim

et al. 2023

Adv Funct Materials

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The ferroelectric negative capacitance (NC) draws a great deal of attention for low‐power negative capacitance field‐effect transistors (NCFET) and NC capacitors. The fabrication of steep‐slope FET (subthreshold swing < 60mVdec−1) is reported, followed by modeling approaches. While the device fabrication favors a ferroelectric gate structure without interlayer metal, many NCFET models adopt interlayer metal between the ferroelectric layer and metal–insulator–semiconductor structure. The metal interlayer averages out spatial variation in the ferroelectric polarization, enabling a compact charge‐based relation between the layers. In addition, the approach assumes that the NC effect emerges from the ferroelectric layer regardless of the metal interlayer, which is not necessarily probable. This work reinvestigates the possible NC effect in ferroelectric–dielectric capacitors connected by a metal interlayer. The experiment confirms that the NC effect in the metal–ferroelectric–dielectric–metal structure does not appear in the metal–ferroelectric–metal–dielectric–metal structure. These results are inconsistent with the multidomain‐1D Landau–Ginzburg‐Devonshire model. In contrast, the suppression of the NC effect in the structure is fully explained by the advanced inhomogeneous stray‐field energy model, which simulates the dynamic evolution of polarization and screening charges. Therefore, an NCFET with a metal interlayer is impractical.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Exploring the Physical Origin of the Negative Capacitance Effect in a Metal–Ferroelectric–Metal–Dielectric Structure

Park,

Byun,

Kim

et al. 2023

Adv Funct Materials

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“…Due to the 60 mV/dec physical limit in subthreshold swing (SS) of conventional MOSFETs at room temperature, it is unrealizable to reduce power consumption by infinitely reducing the supply voltage, which would seriously degrade the circuit performance [1,2].…”

Section: Introductionmentioning

confidence: 99%

A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior

Jiang

2021

Active and Passive Electronic Components

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In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.

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