Emerging On-Chip Interconnect Technologies

Pasricha, Sudeep; Dutt, Nikil

doi:10.1016/b978-0-12-373892-9.00013-x

Cited by 7 publications

(6 citation statements)

References 98 publications

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“…In order to make the AM machine an independent and complete system, we present the inference process as an embedded design. The BNN is implemented in the system on a chip (SoC) [ 30 ], which is the Terasic SoC kit development board as shown in Figure 2 . This board contains an FPGA embedded with an ARM processor, as well as other components such as memory, connectors, sensors, and display.…”

Section: Research Methodsmentioning

confidence: 99%

FPGA-Based Acceleration on Additive Manufacturing Defects Inspection

Luo

Chen

2021

Sensors

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Additive manufacturing (AM) has gained increasing attention over the past years due to its fast prototype, easier modification, and possibility for complex internal texture devices when compared to traditional manufacture processing. However, potential internal defects are occurring during AM processes, and it requires real-time inspections to minimize the costs by either aborting the processing or repairing the defect. In order to perform the defects inspection, first the defects database NEU-DET is used for training. Then, a convolution neural network (CNN) is applied to perform defects classification. For real-time purposes, Field Programmable Gate Arrays (FPGAs) are utilized for acceleration. A binarized neural network (BNN) is proposed to best fit the FPGA bit operations. Finally, for the image labeled with defects, the selective search and non-maximum algorithms are implemented to help locate the coordinates of defects. Experiments show that the BNN model on NEU-DET can achieve 97.9% accuracy in identifying whether the image is defective or defect-free. As for the image classification speed, the FPGA-based BNN module can process one image within 0.5 s. The BNN design is modularized and can be duplicated in parallel to fully utilize logic gates and memory resources in FPGAs. It is clear that the proposed FPGA-based BNN can perform real-time defects inspection with high accuracy and it can easily scale up to larger FPGA implementations.

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Section: Research Methodsmentioning

confidence: 99%

FPGA-Based Acceleration on Additive Manufacturing Defects Inspection

Luo

Chen

2021

Sensors

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“…Each interconnection type Type Link ∈ Types Link has additional characteristics like the transmission energy consumption E transmission : Type Link → N or the transmission delay δ transmission : Type Link → N . Referring back to the design of a multiprocessor system, our concept can model well-known communication structures in System-on-Chip (SoC) design like bus-based communication and Network-on-Chips (NoCs) [34]. On the one hand, for a bus-based communication, we can assign a respective communication type with properties that specify the maximum number of connected devices and the blocking connection arising for the bus-based structure, whereas the respective interconnection types can model the access times and transmission cost for messages.…”

Section: System Modelmentioning

confidence: 99%

Generative Design of the Architecture Platform in Multiprocessor System Design

Müller,

Schumacher,

Steffen

et al. 2024

Electronics

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When designing a system at the Electronic System Level (ESL), designers are confronted with a very large number of design decisions, each affecting the characteristics of the resulting system. Simultaneously, the demands for the system’s performance, reliability, and energy consumption have increased drastically. Design Space Exploration (DSE) aims to facilitate this complex task by automating the system synthesis and traversing the design space autonomously. Previous studies on DSE have mainly considered fixed architectures with a fixed set of hardware components only. In the paper at hand, we overcome this limitation to allow for a higher degree of freedom in the design of a multiprocessor system. Instead of a fixed architecture as input, we are using a resource library containing resource types whose instances can then be arbitrarily placed and connected. More specifically, we enable the exploration of the types, the number, and the positions of required processing-type instances in a grid-based topology template in addition to deciding on the remaining system synthesis tasks, namely, resource allocation, task binding, routing, and scheduling. We provide an extensible framework, based on Answer Set Programming (ASP) modulo Theories (ASPmT), for generating system architectures fulfilling predefined constraints. Our studies show that this higher degree of freedom, originating from fewer restrictions regarding the architecture, leads to an increased complexity of the problem. In extensive experiments, we show scalability trends for a set of parameters, demonstrating the capabilities and limits of our approach.

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“…Additionally, the temporary registers implanted in shared buses usually consume a greater area and higher energy levels, resulting in poor scalability. This is likely to stand as a major hindrance to the maintenance of effective communication via future Multi-Processor Systems on Chip (MPSoC) designs [24][25][26][27][28]. To cater to these needs, Multistage Interconnection Networks (MINs) have emerged as a potential solution for the increasing demand for scalability and reliability in static Network-on-chip (NoC) architectures, to meet the exponential growth in massive parallel computing.…”

Section: Related Workmentioning

confidence: 99%

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

Aydi,

Mnejja,

Mohammed

et al. 2023

Applied Sciences

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In the last few decades, the concept of Wireless Network-on-chip (WiNoC) has emerged as a promising alternative for Multiprocessor Systems on Chip (MPSOC) to achieve reliable and scalable communication. Worth recalling in this regard is that our research team has already designed, verified and evaluated Multistage Interconnection Networks (MIN) in this field. With respect to the present work, we consider proceeding with further exploring our thoughts on this research area. Firstly, we propose the design and performance evaluation of a hybrid (wireless/wired) MIN, analysing how this augmented network can potentially improve not only the average delay, but also energy consumption. Secondly, we continue with examining the implementation of our advanced DELTA-based MIN architecture on Deep Neural Network (DNN) accelerators, while accounting for its potential regularity and scalability in simultaneously maintaining an effective power efficiency and lower latency throughout the DNN operating process. In this context, several metrics have been evaluated in regard to three DNN application cases through implementation of their main respective modules.

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Emerging On-Chip Interconnect Technologies

Cited by 7 publications

References 98 publications

FPGA-Based Acceleration on Additive Manufacturing Defects Inspection

FPGA-Based Acceleration on Additive Manufacturing Defects Inspection

Generative Design of the Architecture Platform in Multiprocessor System Design

Mapping of Deep Neural Network Accelerators on Wireless Multistage Interconnection NoCs

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