Embedded wafer level packages with laterally placed and vertically stacked thin dies

Sharma, Gaurav; Rao, V.S.; Kumar, Aditya; Su, Nandar; Lim, Ying Ying; Houe, Khong Chee; Lim, San Hua; Sekhar, Vasarla Nagendra; Rajoo, R.; Kripesh, V.; Lau, John H.

doi:10.1109/ectc.2009.5074217

Cited by 27 publications

(7 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Earlier development of EMWLP is only 2D integration [3].A new embedded package has been developed that can realize 3D integration with several development processes and materials evaluation and their solutions come out for EMWLP technology. [3,[4][5].…”

Section: Introductionmentioning

confidence: 98%

Low temperature dielectric material for embedded micro wafer level packaging

Rao

Wee

et al. 2009

2009 11th Electronics Packaging Technology Conference

Self Cite

View full text Add to dashboard Cite

In this paper, we have developed the evaluation results of low cure temperature (less than 200 deg C) dielectric materials in terms of process ability and adhesion on SiN and mold compound substrates. The results showed that the low cure temperature dielectric materials have good adhesion on SiN and mold compound substrate. Integration of thin film passives like inductors, capacitors and band pass filters are also demonstrated on this mold compound wafer platform using electroplated Cu and low cure temperature dielectric material. Developed thin film passives on mold compound wafer platform have significantly improved the passives performances that are benchmarked against high resistivity silicon wafer (HiRSi). Reliability test vehicles are fabricated using Cu RDL, low cure temperature dielectric material and electroplated Cu UBM with SAC solder bump interconnects. A complete description of dielectric material evaluation for EMWLP, process development of thin film passive fabrication and multi-layer RDL integration on reconstructed mold compound wafer has been discussed.

show abstract

Section: Introductionmentioning

confidence: 98%

Low temperature dielectric material for embedded micro wafer level packaging

Rao

Wee

et al. 2009

2009 11th Electronics Packaging Technology Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…Institute of microelectronics extended the FOWLP technology to multidie and stacked multidie in 3D format and presented at ECTC2008 [13]. During ECTC2009, Institute of microelectronics presented four papers on: (1) a novel method to predict die shift during compression molding [14]; (2) laterally placed and vertically stacked thin dies [15]; (3) the reliability of 3D FOWLP [16]; and (4) the demonstration of high quality and low-loss millimeter-wave passives on FOWLP [17]. In Refs.…”

Section: Introductionmentioning

confidence: 99%

“…In Refs. [1,3,4,[12][13][14][15][16][17], they used chip-first and die face-down [18] fan-out wafer-level processing.…”

Section: Introductionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

Self Cite

View full text Add to dashboard Cite

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

show abstract

“…The stacked dies are 5mm x 5mm x 0.1mm and 7mm x 7mm x 0.3mm [2]. For wafers thinned down to beyond 100μm, die attach process is a challenge and conventional die attach paste may not be suitable.…”

Section: Introductionmentioning

confidence: 99%

Characterization of DAF tape for embedded micro wafer level packaging

Pei-Siang

Sharma

Kumar

et al. 2009

2009 11th Electronics Packaging Technology Conference

Self Cite

View full text Add to dashboard Cite

The requirements of new packaging technologies for smaller, thinner and lighter electronics products have resulted in electronics industry moving towards wafer level packaging. Some of the main advantages of wafer level packaging are suitability for very fine pitch interconnection, low assembly cost and smaller form factor. This is because the package formed through wafer level technology has the same size as the die itself. Wafer level packaging is in demand especially for portable products such as mobile phone and digital camera. With wafers thinned to 100µm, conventional die attach process may not be suitable as the control of bleed out of the die attached paste becomes critical. New generation of die attach material such as the Dicing Die attach film (DDAF) is introduced to control the paste bleed at the die edge as well as to have a consistent bondline thickness. This paper presents the results of DDAF tape lamination on 100µm thin wafer, DDAF tape dicing process characterization and materials characterization in terms of die shear test of 2 DDAF tapes after die attach process and after subjecting to Moisture Sensitivity test Level 3. A three-factor D.O.E (bonding pressure, bonding temperature and bonding time) adopted to understand the dominant contributing factors on DDAF tape bonding process and to understand the effects of bonding parameters on the DDAF bondline thickness and DDAF voids (Table 1). The 3 selected bond forces range from 0.5kg to 2.5kg. Reliability of the DDAF assembly will also be studied and reported in this work.

show abstract

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Cited by 27 publications

References 8 publications

Low temperature dielectric material for embedded micro wafer level packaging

Low temperature dielectric material for embedded micro wafer level packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Characterization of DAF tape for embedded micro wafer level packaging

Contact Info

Product

Resources

About