Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor

Severance, Aaron; Lemieux, Guy

doi:10.1109/codes-isss.2013.6658993

Cited by 45 publications

(41 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Overlays come in many forms, with the most common being spatially configured [9], [6] and time multiplexed (TM) [24], [16]. Spatially configured overlays fully unroll the kernel onto a pipelined array of FUs, resulting in an initiation interval (II) of 1.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A time-multiplexed FPGA overlay with linear interconnect

Jain

Maskell

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

Coarse-grained overlays improve FPGA design productivity by providing fast compilation and software like programmability. Soft processor based overlays with well-defined ISAs are attractive to application developers due to their ease of use. However, these overlays have significant FPGA resource overheads. Time multiplexed (TM) CGRA-like overlays represent an interesting alternative as they are able to change their behavior on a cycle by cycle basis while the compute kernel executes. This reduces the FPGA resource needed, but at the cost of a higher initiation interval (II) and hence reduced throughput.The fully flexible routing network of current CGRA-like overlays results in high FPGA resource usage. However, many application kernels are acyclic and can be implemented using a much simpler linear feed-forward routing network. This paper examines a DSP block based TM overlay with linear interconnect where the overlay architecture takes account of the application kernels' characteristics and the underlying FPGA architecture, so as to minimize the II and the FPGA resource usage. We examine a number of architectural extensions to the DSP block based functional unit to improve the II, throughput and latency. The results show an average 70% reduction in II, with corresponding improvements in throughput and latency.

show abstract

Section: Related Workmentioning

confidence: 99%

“…Most successful TM overlays are based on soft processors. The more performance oriented ones include, SIMD Octavo [13], VectorBlox MXP [24] and VLIW TILT [19]. A massively parallel overlay, called GRVI Phalanx [7], based on the RISC-V processor and the Hoplite NOC [11] mapped 1680 RISC-V cores onto an UltraScale+ VU9P.…”

Section: Related Workmentioning

confidence: 99%

A time-multiplexed FPGA overlay with linear interconnect

Jain

Maskell

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…While VIPERS, VESPA, VEGAS, VENICE and BlueVec operate on integer data, the vector architecture presented in [7] works with floating-point operands. For our experiments, we use the MXP [12] soft vector processor with supports integer and fixed-point calculations only. While existing vector archi tectures offer superior performance when using FPGA logic, the performance comparisons have always been against other soft processors with poor performance e.g.…”

Section: Contextmentioning

confidence: 99%

“…To retain the fast development times and performance of mapping to NEON, we consider the Vectorblox MXP [12] soft vector processor as the alternative implementation. MXP is an FPGA-based soft vector processor designed to perform data-parallel tasks with high performance.…”

Section: Introductionmentioning

confidence: 99%

Comparing soft and hard vector processing in FPGA-based embedded systems

Jie

Kapre

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

Soft vector processors can augment and extend the capability of embedded hard vector processors in FPGA-based SoCs such as the Xilinx Zynq. We develop a compiler framework and an auto-tuning runtime that optimizes and executes data-parallel computation either on the scalar ARM processor, the embedded NEON engine or the Vectorblox MXP soft vector processor as appropriate. We consider computational conditions such as pre cision, vector length, chunk size, 10 requirements under which soft vector processing can outperform scalar cores and hard vector blocks. Across a range of data-parallel benchmarks, we show that the MXP soft vector processor can outperform the NEON engine by up to 3.95 x while saving 9% dynamic power (0.1 W absolute). Our compilation and runtime framework is also able to outperform the gcc NEON vectorizer under certain conditions by explicit generation of NEON intrinsics and performance tuning of the auto-generated data-parallel code.

show abstract

“…A number of overlay architectures have been proposed, including ZUMA [16][17], iDEA [18], MXP [19], Octavo [20], VLIW-SCORE [21], Soft-CGRA [22], and…”

Section: Overlay Architecturesmentioning

confidence: 99%

Rapid Overlay Builder for Xilinx FPGAs

Yue

Koch

Lemieux

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

Self Cite

View full text Add to dashboard Cite

A field-programmable gate array (FPGA) is a type of programmable hardware, where a logic designer must create a specific hardware design and then "compile" it into a bitstream that "configures" the device for a specific function at power-up. This compiling process, known as place-and-route (PAR), can take hours or even days, a duration which discourages the use of FPGAs for solving compute-oriented problems. To help mitigate this and other problems, overlays are emerging as useful design patterns in solving compute-oriented problems. An overlay consists of a set of compiler-like tools and an architecture written in a hardware design language like VHDL or Verilog. This cleanly separates the compiling problem into two phases: at the front end, high-level language compilers can quickly map a compute task into the overlay architecture, which is now serving as an intermediate layer. Unfortunately, the back-end of the process, where an overlay architecture is compiled into an FPGA device, remains a very time-consuming task. Many attempts have been made to accelerate the PAR process, ranging from using multicore processors, making quality/runtime tradeoffs, and using hard macros, with limited success. We introduce a new hard-macro methodology, called Rapid Overlay Builder, and demonstrate a run-time improvement up to 22 times compared to a regular unaccelerated flow using Xilinx ISE. In addition, compared to prior work, ROB continues to work well even with high logic utilization levels of 89%, and it consistently maintains high clock rates. By applying this methodology, we anticipate that overlays can be implemented much more quickly and with lower area and speed overheads than would otherwise be possible. This will greatly improve the usability of FPGAs, allowing them to be used as a replacement for CPUs in a greater variety of applications.

show abstract

Embedded supercomputing in FPGAs with the VectorBlox MXP Matrix Processor

Cited by 45 publications

References 9 publications

A time-multiplexed FPGA overlay with linear interconnect

A time-multiplexed FPGA overlay with linear interconnect

Comparing soft and hard vector processing in FPGA-based embedded systems

Rapid Overlay Builder for Xilinx FPGAs

Contact Info

Product

Resources

About