Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

Chindalore, G.; Yater, J.A.; Gasquet, H.; Suhail, M.; Kang, Sung-Taeg; Hong, Cheong Min; Ellis, N.; Rinkenberger, G.; Shen, Juan; Herrick, M.; Malloch, W.; Syzdek, R.; Baker, K.; Chang, Ko-Min

doi:10.1109/vlsit.2008.4588592

Cited by 10 publications

(6 citation statements)

References 1 publication

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“…4 Nanocrystal memory array For successful memory product introduction, individual nanocrystal bitcells must perform repeatably when built in an array of thousands or millions of bytes [25]. Each bitcell must program to a verify level in a defined write time, and erase to a verify level in a defined erase time, as illustrated in Fig.…”

Section: Bitcell Operationmentioning

confidence: 99%

Implementation of Si nanocrystals in non-volatile memory devices

Yater¹

2013

Phys. Status Solidi A

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Growth in the demand for flash non-volatile memory (NVM) has been driven by mass storage applications, as well as mobile and consumer electronics. Embedded flash is utilized in microcontrollers where system speed, security, and customization are important. The challenges of embedded flash memories, usable across a range of products from consumer to automotive, include the ability to store and update data over a wide range of temperature and voltage corners. Nanocrystal memory is of great interest because of its improved reliability due to the localized nature of the charge storage, as well as its process simplicity and ease of integration into the complementary metal-oxide-semiconductor (CMOS) platform. Additionally, scaling of the dielectric thickness allows for reduced operating voltages and module size. Nanocrystal deposition techniques have been developed to produce uniform, controllable films, and device performance is well-behaved. The first commercially available microcontroller family built with silicon nanocrystals as the storage medium is now in production, built on a 90 nm platform and using a split-gate architecture. In this work, device and materials issues related to silicon nanocrystal memory are reviewed, and memory array performance discussed. Finally, scalability of nanocrystal memories is considered, where excellent performance and reliability can be achieved down to the 40 nm technology node and further.

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Section: Bitcell Operationmentioning

confidence: 99%

Implementation of Si nanocrystals in non-volatile memory devices

Yater¹

2013

Phys. Status Solidi A

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“…Split-gate flash memory has been widely studied for embedded memory applications thanks to its high programming efficiency, low power consumption and immunity to over-erase problem. [1][2][3][4][5][6][7][8][9][10][11] Source-side injection (SSI) of hot electrons is most commonly utilized to program the cell because both high lateral and vertical field are obtained in the gap region with proper bias. 1) The charge-storage layer of split-gate memory can be floating poly, nitride 9) or nanocrystal.…”

Section: Introductionmentioning

confidence: 99%

“…1) The charge-storage layer of split-gate memory can be floating poly, nitride 9) or nanocrystal. 11) For split-gate memory cell with floating poly, it can be erased by uniform channel Fowler-Nordheim (FN) erase, 3) source-junction-side FN erase, 2) or poly-topoly FN erase. 5) In ref.…”

Section: Introductionmentioning

confidence: 99%

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Zhao¹,

He²,

Huang³

et al. 2010

Jpn. J. Appl. Phys.

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We explore the conjectured duality between the critical O(N) vector model and minimal bosonic massless higher spin (HS) theory in AdS. In the free boundary theory, the conformal partial wave expansion (CPWE) of the four-point function of the scalar singlet bilinear is reorganized to make it explicitly crossing-symmetric and closed in the singlet sector, dual to the bulk HS gauge fields. We are able to analytically establish the factorized form of the fusion coefficients as well as the two-point function coefficient of the HS currents. We insist in directly computing the free correlators from bulk graphs with the unconventional branch. The three-point function of the scalar bilinear turns out to be an "extremal" one at d = 3. The four-point bulk exchange graph can be precisely related to the CPWs of the boundary dual scalar and its shadow. The flow in the IR by Legendre transforming at leading 1/N, following the pattern of double-trace deformations, and the assumption of degeneracy of the hologram lead to the CPWE of the scalar fourpoint function at IR. Here we confirm some previous results, obtained from more involved computations of skeleton graphs, as well as extend some of them from d = 3 to generic dimension 2 < d < 4.

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“…The difficulty in scaling the tunnel oxide (TO) thickness due to stress-induced leakage-current-related charge loss, reduction in gate coupling, and increase in cell-to-cell interference have made scaling of FG flash difficult at sub-3× node [2]. Nanocrystal (NC) flash [3]- [12] and charge trap flash (CTF) [13], [14] are considered as possible alternatives. CTF devices reported so far show good memory window but poor retention [13], [14], while the NC devices show poor memory window [4], [6], [11], [12].…”

mentioning

confidence: 99%

“…Previously reported small memory window of the NC devices can be attributed to nonoptimal NC number density (ND), size distribution, small area coverage (AC), and low NC WF or high control dielectric (CD) leakage. A significant amount of work on NC-based Flash memory structures has focused on semiconductor NCs like Si [3] and Ge [4]. Issues with semiconductor-based NCs are small WF, quantum-confinement (QC)-related WF lowering, and poor control of NC size that result in poor overall performance of such devices.…”

mentioning

confidence: 99%

Performance and Reliability of Au and Pt Single-Layer Metal Nanocrystal Flash Memory Under nand (FN/FN) Operation

Singh

Hofmann

Singh

et al. 2009

IEEE Trans. Electron Devices

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Abstract-In this paper, we report on the fabrication and reliability characterization of gold (Au) and platinum (Pt) single-layer nanocrystal (NC)-based Flash memory devices for NAND application. The devices are fabricated using a CMOS-compatible process flow with high-quality (low leakage and large breakdown) Al 2 O 3 as the control dielectric. The impact of processing conditions on the NC size, area coverage, and number density is also investigated. Large memory window (∼7.5 V for Au and ∼10 V for Pt) and good retention are observed for both Au and Pt NC devices. Excellent postcycling retention is also noted for Pt NC devices. Endurance characteristics are found to be of concern as maximum of only 1 × 10 3 and 4 × 10 3 cycles can be obtained for Au and Pt devices, respectively. Anneal-temperature-dependent gate leakage is observed in Au devices and is investigated using analytical methods. Diffusion of Au atoms from the NC into the gate dielectrics is seen which correlates to the electrical measurements. Postcycling retention and program/erase of Pt NC devices are shown to be good.Index Terms-Cycling endurance, Flash memory, memory window, metal nanocrystals (NCs), reliability failure, retention, transmission electron microscopy (TEM)/electron diffraction (EDX).

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Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

Cited by 10 publications

References 1 publication

Implementation of Si nanocrystals in non-volatile memory devices

Implementation of Si nanocrystals in non-volatile memory devices

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Performance and Reliability of Au and Pt Single-Layer Metal Nanocrystal Flash Memory Under nand (FN/FN) Operation

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