Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

Zhang, D.; Nguyen, Bich‐Yen; White, T.; Goolsby, Brian; Nguyen, Thien Huu; Dhandapani, V.; Hildreth, J.; Foisy, M.; Adams, V.; Shiho, Y.; Thean, A.; Theodore, D.; Canonico, M.; Zollner, Stefan; Bagchi, S.; Murphy, Sharon Ann; Rai, R.; Jiang, Jin; Jahanbani, M.; Noble, R.; Zavala, M.; Cotton, R.; Eades, D.; Parsons, S.; Montgomery, Patrick K.; Martínez, Arturo; Winstead, B.; Mendicino, M.; Cheek, J.; Liu, J.; Grudowski, P. A.; Ranami, N.; Tomasini, P.; Arena, C.; Werkhoven, C.; Kirby, H.; Chang, Chih-Sheng; Lin, C.T.; Tuan, H.C.; See, Y.C.; Venkatesan, S.; Kolagunta, V.; Cave, N.; Mogab, J.

doi:10.1109/.2005.1469198

Cited by 18 publications

(7 citation statements)

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“…Even if the isotropic recess etch can be achieved, Si migration may also become a problem for such thin Si fins during the SiGe epitaxy process. 9) The oxidation of SiGe in the (110) surface orientation is also observed to be faster when compared to the (100) surface orientation. By optimizing the process and the dimensions of the fin, it is also possible to achieve a higher Ge concentration at the S/D regions due to the piling up of Ge atoms, 10) thereby enhancing the effect of strain further.…”

Section: Resultsmentioning

confidence: 98%

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Tan

Liow

Lee

et al. 2007

jjap

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Strained p-channel fin-type field-effect transistors (FinFETs) with SiGe source and drain (S/D) regions formed by a Ge condensation process is demonstrated. SiGe epitaxial layer was grown on the sidewalls at the S/D regions after a successful removal of both the polysilicon gate and nitride spacer stringer. Condensation of the SiGe at the S/D region was subsequently performed. The novel local Ge condensation not only drives Ge into the Si fin and/or increases the Ge concentration in the S/D regions for enhanced strain effects, but also eliminates the need for S/D recess etch, leading to process simplicity. Compared to a FinFET with uncondensed Si 1Àx Ge x S/D, FinFETs with condensed Si 1Ày Ge y S/D exhibit 28% higher drive current. Devices with gate lengths down to 26 nm were demonstrated with excellent control of short-channel effects.

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Section: Resultsmentioning

confidence: 98%

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Tan

Liow

Lee

et al. 2007

jjap

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“…For example, the on-current of an n-type field-effect transistor can be increased by applying residual stress on the Si channel using a tensile capping layer [13,14]. Also, the carrier mobility of the transistor can be increased by using lattice-mismatched materials (e.g., SiGe) which can induce residual stress in the source/drain regions [15,16].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Residual Stresses Induced in the Confined 3D NAND Flash Memory Structure for Process Optimization

Jang

Kim

Lee

et al. 2022

IEEE J. Electron Devices Soc.

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“…Therefore, to improve both the electron mobility in n-channel MOSFETs (n-FETs) and the hole mobility in p-channel MOSFETs (p-FETs), the introduction of strain in the transistor channel needs to employ different approaches for n-FETs and p-FETs (table 1). Existing techniques take advantage of the stress due to the SiN liner or contact etch-stop layer [2][3][4], SiGe source/drain (S/D) regions [4][5][6][7][8][9][10][11][12], shallow trench isolation [13], or other process-induced effects, e.g. stress memorization technique [14].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we explore the enhancement of transistor performance using source/drain materials that are lattice-mismatched with respect to the silicon channel. Materials such as silicon-carbon (Si 1−y C y ) [15,16] and silicon-germanium (Si 1−x Ge x ) [4][5][6][7][8][9][10][11][12] have lattice constants smaller than and larger than that of silicon, respectively. We investigate the use of these materials to engineer the lattice strain in the transistor channel region for the improvement of electron and hole mobilities in n-FET and p-FET, respectively (figure 1).…”

Section: Introductionmentioning

confidence: 99%

Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions

Yeo

2006

Semicond. Sci. Technol.

115

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We explore several technology options for the enhancement of electron and hole mobility in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, focusing on strain engineering using lattice-mismatched source/drain (S/D) materials. Silicon-carbon (Si 1−y C y ) and silicon-germanium (Si 1−x Ge x ) have lattice constants different from that of the Si channel. When Si 1−y C y or Si 1−x Ge x is embedded in the transistor S/D region, lateral tensile or compressive strain is induced in the adjacent Si channel, leading to improvement in the electron or hole mobility, respectively. The origin of the strain effect, process integration, device characteristics and strain enhancement approaches are discussed.

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Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

Cited by 18 publications

References 0 publications

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Sub-30 nm Strained p-Channel Fin-Type Field-Effect Transistors with Condensed SiGe Source/Drain Stressors

Analysis of Residual Stresses Induced in the Confined 3D NAND Flash Memory Structure for Process Optimization

Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions

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