Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines

Abstract

Abstract-Cascade

An energy-efficient parallel VLSI architecture for SVM classification

“…Some methods aim to obtain a similar but easy-implementing model by adjusting its parameters, such as parameters of classifiers are rounded off to the nearest power of two values and multipliers in the corresponding hardware design are replaced with shift operations to reduce both area and power [2]. However, it has a negative impact on the performance of classifiers in many applications.…”

“…Some methods aim to find a simple and suitable classifier in specialized applications, such as two linear SVM-based classifiers instead of a non-linear SVM-based classifier are utilized to enhance both the sensitivity and specificity simultaneously in the patient-specific application [3]. There are also some methods aiming to improve the structure of classifiers, such as a cascaded classifier is put forward for applications where data distribution is between-class imbalanced [2,4,5]. In this situation, multiple SVM-based classifiers with various performance are arranged in order according to the computational complexity as well as accuracy.…”

Hardware Acceleration of SVM-Based Classifier for Melanoma Images

“…Interestingly, many studies adopted the multiplier-less approach [9], [12,13,14], where expensive multipliers required for computations are replaced with conventional adders and/or shifters in order to decrease hardware complexity. Similarly, others [15,16] utilized the hardware-friendly kernel function for simplifying the hardware design by using also the simple shift and add operations instead of resource consuming multiplications.…”

“…As a result of multiplier-less implementation, significant reduction in hardware resources utilization was achieved. In addition, remarkable power consumption decrease was demonstrated [9], [12,13], [17].…”

“…Moreover, the common pipelining technique was used in many previous hardware designs [11,12,13], [17,18,19,20,21,22,23,24,25,26], taking advantage of the parallel processing capabilities of the FPGA that led to throughput increase of the implemented classification process. Some researchers designed a pipeline stage for common and shared multipliers required for computations to decrease usage of duplicate multiplications [19,20].…”