Hardware Acceleration of SVM-Based Classifier for Melanoma Images

Abstract

Abstract. Melanoma is the most aggressive form of skin cancer which is responsible for the majority of skin cancer related deaths. Recently, image-based Computer Aided Diagnosis (CAD) systems are being increasingly used to help skin cancer specialists in detecting melanoma lesions early, and consequently reduce mortality rates. In this paper, we implement the most compute-intensive classification stage in the CAD onto FPGA, aiming to achieve acceleration of the system for deploying as an embedded device. A hardware/software co-design approach was proposed for implementing the Support Vector Machine (SVM) classifier for classifying melanoma images online in real-time. The hybrid Zynq platform was used for implementing the proposed architecture of the SVM classifier designed using the High Level Synthesis design methodology. The implemented SVM classification system on Zynq demonstrated high performance with low resources utilization and power consumption, meeting several embedded systems constraints.

Supervised learning methods for pathological arterial pulse wave differentiation: A SVM and neural networks approach

“…Kernel functions are responsible to implicitly map non-linear features into a high-dimensional features space and use linear approaches for solving learning and estimation issues. This type of classifier has been widely used in several biomedical problems with great success [66,67], [71][72][73][74][75]. SVM is currently considered, for example, the most suitable type of classifier for ECG-based biometric applications [65,76].…”

“…SVM is currently considered, for example, the most suitable type of classifier for ECG-based biometric applications [65,76]. Additionally, several authors have so far proved that SVMs are suitable to be embedded in low-cost wearable hardware modules for physiological monitoring [73,[77][78][79].…”

FPGA Implementations of SVM Classifiers: A Review

“…The High-level Synthesis (HLS) design methodology has been recently used to decrease the FPGA development time and effort by using HLLs instead of HDLs. The Xilinx Vivado HLS tool [58] is exploited to implement a low-cost SVM IP [59][60][61][62][63][64] on a recent FPGA platform "Zynq SoC" with a hybrid architecture combining a processor with the FPGA in a single device [65]. An initial hardware/software co-design is implemented in [59] as an SVM accelerator to run the complicated processing task onto FPGA.…”

“…Only four researchers utilize the recent Xilinx series-7 devices [23,31,51,55]. One unique research work is discriminated by exploiting the hybrid architecture of the recent Zynq-7 SoC platform and using the latest UltraFast HLS design methodology [59][60][61][62][63][64] followed by a recent study for design space exploration based on SVM implementation in [66,67].…”

“…Group 3: An interesting and unique research work is presented by another research group led by S. Afifi [59][60][61][62][63][64] which exploit the most recent hybrid Zynq SoC platform and the modern UltraFast HLS design methodology (category E). They develop the first HLS SVM IP/core on Zynq SoC exists in literature targeting low-cost and real-time melanoma detection.…”