Embedded Ferroelectric Memory Technology With Completely Encapsulated Hydrogen Barrier Structure

Abstract

A 0.18-m system LSI embedded ferroelectric memory (FeRAM) operating at a very low voltage has been developed for the first time. The low-voltage operation has been attained by newly developed stacked ferroelectric capacitors completely encapsulated by hydrogen barriers, which enable us to eliminate hydrogen reduction of the ferroelectric thin film during the back end of the line process including FSG, tungsten CVD (W-CVD), and plasma CVD SiN (p-SiN) passivation. A fabricated 1-Mbit one-transistor one-capacitor SrBi 2 (Ta x Nb 1 x ) 2 O 9 (SBTN)-based embedded FeRAM operates at a low voltage of 1.1 V and ensures the endurance cycles up to 10 12 at 85 C and the data retention time up to 1000 h at 125 C, which is the most promising for mass production of 0.18-m low-power system LSI-embedded FeRAM and beyond.Index Terms-Ferroelectric memory, hydrogen barrier, low-voltage operation, reliability.

Overview and Future Challenge of Ferroelectric Random Access Memory Technologies

“…1(a)]. 5) As ferroelectric capacitors are stacked on pass transistors, 6) microprobing on the electrodes of the pass transistors would destroy the data stored in the ferroelectric capacitors [Fig. 1(b)].…”

“…To improve the density of configuration memories, we have implemented ferroelectric memory cells composed of two SBT capacitors and two pass transistors in a reconfigurable circuit by 0.18 mm FeRAM technology. 6) Figure 5 shows a block diagram of the fabricated reconfigurable circuit consisting of a 16 Â 32 functional unit (FU) array and routing interconnects (RIs). The reconfigurable circuit can perform one of the eight different functions, such as encryption, decryption, and communication protocols, on the basis of the configuration data stored in the ferroelectric memories.…”

“…At the 0.18 mm node, a planar capacitor surrounded by a hydrogen barrier is stacked on a pass transistor, which withstands hydrogen attacks during a CMOS back-end process. 6) The memory cell size is then dominated by the capacitor area. As the planar capacitor is not allowed for much tighter density transistors at the 130 nm node, a three-dimensional (3D) capacitor structure is required to reduce a footprint.…”

Fast Pulse Driving of Ferroelectric SBT Capacitors in a Nonvolatile Latch

“…Therefore, we aimed at developing a fast transition of a logic status by connecting directly the drive circuit with an individual ferroelectric capacitor, and minimizing parasitic resistance and capacitance. In order to investigate the improved fast transition time, using 0.18-µm FeRAM technology [16], we designed and fabricated NVLTs where drive circuits are directly con- nected to SBT ferroelectric capacitors in the NVLTs. Area of an SBT capacitor is 1.2 µm 2 and SBT film thickness is 100 nm.…”

CMOS Technology Toward Green

“…Electric Memory (FeRAM) FeRAM(28)(29)(30) based on ferro-electric polarization in capacitor has advantages in low-power and low-voltage (~1v) operations, high write endurance (~1012 ), and fast programming (<100ns). Conventional ferro-electric materials include families of PZT(PbZr x Ti x O 3 ), SBT (SrBi 2 Ta 2 O 9 ), BTO (Bi 4 Ti 3 O 12 ), …etc with desirable properties of fatigue-free, imprint-free, low process temperature, good retention, and high remnant polarization.…”