The purpose of this chapter is to set the stage on which the rest of this book plays out. We describe the technology that we work with, in the form of the SDRAM chips that external companies produce for us (and the rest of the world) in Sect. 2.1. Because, the same SDRAM chips are used by everyone, it is not surprising that most memory controllers, i.e., the interfaces that interact with these chips, have at least the same high-level structure, as introduced earlier in Sect. 1.2. For the sake of efficiency, the proverbial wheel tends to be invented only a few times before the interested community settles for a design that works in most cases. Further improvements are driven by the needs of specific application areas and the gradual evolution of the surrounding actors and requirements. This book focuses on the area of mixed timecriticality systems, and uses an existing SDRAM controller template for real-time systems, the pattern-based controller [1], as its starting point. The properties of this controller are introduced in Sect. 2.2.The story continues with a detailed description of our novel reconfigurable memory controller architecture in Sect. 2.3. It partially concerns the introduction of concepts and structures used in the controller, and touches upon some of the real-time aspects that are influenced by its structure and implementation. This controller is the framework on which the other contributions in this book are pinned. The memory patterns we generate in Chap. 3 are stored within this controller. The analysis from Chap. 4 and the trade-offs we describe in Chap. 5 apply to memory controllers that follows the architecture template we describe here, and the conservative open-page policy in Chap. 6 is implemented on a slightly modified version of the same template. The embedded reconfiguration hardware enables the controller to adapt to different use-cases as we describe in Chap. 7.In Sect. 2.4, we derive a worst-case performance model for this memory controller architecture, based on a Latency-rate (LR) server abstraction. This performance model applies to many well known arbiters and can be used in frameworks that enable system-level analysis. We then continue with a discussion on the implementation of a hardware instance on Field Programmable Gate Array (FPGA) in Sect. 2.5, which demonstrates that this memory controller is not only conceptually sound, but really works when it is connected to a real SDRAM module and integrated
SDRAMSDRAM is an extremely popular type of memory. DRAMExchange (a market analyst) reports that in February 2015 alone, 2.4 billion 2 gibibit (2 30 ) equivalent units were produced worldwide [3], for a total capacity of 5.16 exabits. This amounts to a production rate of 267 GB/s, 1 a relatively modest "bandwidth" that about 100 combined contemporary SDRAM devices (single chips) could easily deliver in the worst case, as we later show in Chap. 5.SDRAM is volatile and used as temporary data storage, similarly to caches or Static Random-Access Memory (SRAM) memories. It only stores d...
