Virtual execution platforms for mixed-time-criticality systems

Abstract

Systems on chip (SOC) contain multiple concurrent applications with different time criticality (firm, soft, non real-time). As a result, they are often developed by different teams or companies, with different models of computation (MOC) such as dataflow, Kahn process networks (KPN), or time-triggered (TT). SOC functionality and (real-time) performance is verified after all applications have been integrated. In this paper we propose the CompSOC platform and design flows that offers a virtual execution platform per application, to allow independent design, verification, and execution . We introduce the composability and predictability concepts, why they help, and how they are implemented in the different resources of the CompSOC architecture. We define a design flow that allows real-time cyclo-static dataflow (CSDF) applications to be automatically mapped, verified, and executed. Mapping and analysis of KPN and TT applications is not automated but they do run composably in their allocated virtual platforms. Although most of the techniques used here have been published in isolation, this paper is the first comprehensive overview of the CompSOC approach. Moreover, three new case studies illustrate all claimed benefits: 1) An example firm-real-time CSDF H.263 decoder is automatically mapped and verified. 2) Applications with different models of computation (CSDF and TT) run composably. 3) Adaptive soft-real-time applications execute composably and can hence be verified independently by simulation.

Programming and analysing scenario-aware dataflow on a multi-processor platform

“…We mapped an application onto the CompSOC platform to demonstrate our concept and implementation [9]. The available libDataflow and libFIFO libraries implement dataflow execution and first-in first-out (FIFO) channels.…”

“…Thirdly, connecting multiple actors to one FIFO that holds a persistent token requires no changes but reduces the memory footprint. SDF 3 can analyse and map SDF and cyclo-static dataflow (CSDF) applications onto a CompSOC platform using an HSDF platform model [9], [10]. In the context of this work we extended the HSDF platform model for FSM-SADF analysis.…”

“…Each processor features instruction and data memories of 256 kB each as well as one DMA with two communication memories of 16kB each. The processors are connected to each other and to an external DDR memory via a NoC [9].…”

Invasive computing for timing-predictable stream processing on MPSoCs

“…This significantly reduces the effort of verifying the real-time properties of the system as not all possible scenarios have to be tested. Rather, the system designer assembles the system by combining the verified software components at design time [10].…”

Composable Platform-Aware Embedded Control Systems on a Multi-core Architecture

“…Using a time-division multiplex (TDM) based policy in the platform is one possible option to achieve composability. As an implementation platform, we consider an existing platform -Composable and Predictable System on Chip (CompSOC)-that uses a TDM based policy to achieve composability [7]. In this work, we study an efficient implementation of feedback control systems onto such composable platforms.…”