Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling

Joynson, R. E.; Mundy, Joseph L.; Burgess, James; Neugebauer, C. A.

doi:10.1109/jssc.1972.1050280

Cited by 20 publications

(3 citation statements)

References 1 publication

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“…The shift register drives the output signals by single-phase 10-V clocks (ck/ckb), and they are leveled down to -8 V in order to address 0-5 V analog data from the source driver. The proposed levelshifter as well as a shift register employs the bootstrap technique 15 for the pull-down switching and requires only three supply voltages (10, 0, -8 V).…”

Section: P-type Panel Integrationmentioning

confidence: 99%

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Nam

Lee

et al. 2006

J Soc Info Display

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Abstracts -P-type low-temperature (450°C) polycrystalline-silicon thin-film-transistor circuits for peripheral driver integration in active-matrix displays are proposed and verified. A low-voltage (5 V) driven poly-Si scan driver is designed by employing a level shifter and shift register. A source driver for six-bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D′) without an output voltage loss. A new source-follower type analog buffer is developed and exhibits a small offset deviation regardless of the V TH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p-type panel integration. FIGURE 1 -P-type poly-Si TFT panel integration: (a) analog interface using the demultiplexing block drive and (b) proposed p-type integration for digital interface.

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Section: P-type Panel Integrationmentioning

confidence: 99%

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Nam

Lee

et al. 2006

J Soc Info Display

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“…9) Figure3(b) shows the measurement results and the operation of level-up voltage shifter is accomplished successfully. The channel W=L sizes are M1-M4 (10/8 mm) and M5-M6 (40/ 8 mm).…”

mentioning

confidence: 94%

“…8) In order to eliminate the output voltage loss in p-type pull-down switching, we employ bootstrapping by which the electrically float node is capacitively coupled by input voltage. 9) Figure 2 shows a proposed digital switch using p-type transistors, where T1 is pull-down and T2 is pull-up transistor for V SS and V DD respectively. When SW1 is 10 V and SW2 is 0 V, the T2 and T4 turned off.…”

mentioning

confidence: 99%

Low-Voltage Driven P-Type Polycrystalline Silicon Thin-Film Transistor Integrated Gate Driver Circuits for Low-Cost Chip-on-Glass Panel

Nam

Lee

Shin

et al. 2006

jjap

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P-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) integrated driver circuits are proposed for low-cost chip-on-glass (COG) panel. In order to reduce the process cost of panel, gate driver employing level-shifter, shift register and DC-DC converter is integrated by p-type polycrystalline silicon (poly-Si) TFTs. The gate drivers are composed of the level-up and level-down voltage shifters and the robust two-clock shift registers. The DC-DC converters are designed using diode-connected type charge pumps and regulators. The proposed p-type circuits were verified successfully by the simulations and the measurements.

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Bootstrap Circuits

Embabi¹

1999

Wiley Encyclopedia of Electrical and Electronics Engineering

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Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling

Cited by 20 publications

References 1 publication

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Peripheral circuit designs using low‐temperature p‐type poly‐Si thin‐film transistors

Low-Voltage Driven P-Type Polycrystalline Silicon Thin-Film Transistor Integrated Gate Driver Circuits for Low-Cost Chip-on-Glass Panel

Bootstrap Circuits

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