Electron Trap Generation in High-<tex>$kappa$</tex>Gate Stacks by Constant Voltage Stress

Abstract

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO 2 /HfO 2 /TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO 2 layer (IL) or high-κ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO 2 layer. The generated traps can be passivated by a forming gas or nitrogen (N 2 ) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-κ stacks.

The Pulsed Id-Vgmethodology and Its Application to the Electron Trapping Characterization of High-κ gate Dielectrics

“…In addition to fast transient mechanisms, slow trapping and/or trap generation can impact V t instability in high-κ transistors when constant voltage stress is measured [22,25,30,34,84,88,89,105]. The oxygen vacancy defects responsible for the FTCE have also been found to exhibit a temperature-activated slow migration of trapped electrons to unoccupied traps [50,74].…”

Direct observation of electrically active interfacial layer defects which may cause threshold voltage instabilities in HfO2 based metal-oxide-silicon field-effect transistors

“…3,4 Several studies indicate that trapping centers in the "bulk" of HfO 2 is of particular concern; 3,4 however, recent studies clearly indicate that near Si/dielectric trapping centers ͓centers within the Si/dielectric interfacial layer ͑IL͔͒ play additional important roles in Si/ HfO 2 device instabilities. 5,6 Little is known about the structural nature of these performance limiting defects.…”

Radiation Induced Charge Trapping in Ultrathin ${\rm HfO}_{2}$-Based MOSFETs

“…Constant voltage stress (CVS) studies were performed on time scales comparable to those required for the 10 irradiations. These tests were performed to separate the contributions of bias-induced charge trapping/creation [36] in these oxides from radiation-induced shifts. There were no significant changes in the subthreshold curve stretchout for the irradiation or stress results reported here, as illustrated below.…”