Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures

Kim, Tae Hun; Park, Il Han; Lee, Jong Duk; Shin, Hyun-Chool; Park, Byung‐Gook

doi:10.1063/1.2335619

Cited by 65 publications

(40 citation statements)

References 4 publications

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“…These values indicate a reduction in electron trap depth as the SiN becomes Si + . This is consistent with the existing literature [20], which also attributes the increase in charge loss to relatively shallower trap energy levels in Si + SiN. Fig.…”

Section: Sin Compared To Sisupporting

confidence: 82%

“…9(b) shows the trends, with the V FB shifts measured at the end of 10 4 s. A strong dependence of retention charge loss on the SiN composition is observed. A progressive increase in electron loss from the P state is observed as the SiN composition is varied from N + (N1) to Si + (N4), which is similar to [20]. The E state shows the opposite trend with larger loss observed in relatively N + …”

Section: Intrinsic Retention Performancementioning

confidence: 51%

“…For example, when N4 (Si + ) is compared to N1 (N + ) at identical P/E conditions, although the P state level reduces by 14%, it is compensated by a remarkable decrease in E state level, resulting in a 38% increase in the overall window. A reduction in P state level is observed in Si + SiN despite it being known to have a higher trap density [20]. This is attributed to the increased charge detrapping, owing to shallower trap energy levels, resulting in net lower P saturation level, as explained in [33].…”

Section: A Constant-voltage P/e Transientsmentioning

confidence: 94%

“…It has also been shown [20], [21] that the Sirich (Si + ) SiN has higher electron trap density at relatively shallow energy levels, allowing them to get readily discharged of the electrons during E operations [22]. In our earlier letter, it has been demonstrated that Si + SiN and N + SiN show several interesting tradeoffs in P/E windows, retention and endurance characteristics from both P and E states [22].…”

Section: Introductionmentioning

confidence: 99%

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Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2009

IEEE Trans. Electron Devices

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Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

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Section: Sin Compared To Sisupporting

confidence: 82%

Section: Intrinsic Retention Performancementioning

confidence: 51%

Section: A Constant-voltage P/e Transientsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2009

IEEE Trans. Electron Devices

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“…N1 and N2 (N + SiN) stacks show higher saturation level compared to N3 and N4 (Si + SiN), the differences being more apparent at higher program V G . Lower program saturation level for Si + SiN has been explained by the increased emission of charges trapped in shallow energy levels, resulting in reduced trapping efficiency [32]. On the other hand, the overerase capability (natural V FB ∼ 0 V for all stacks) progressively increases from the most N + SiN (N1) to the most Si + SiN (N4).…”

Section: A Effect Of Sin Composition On P/e Performancementioning

confidence: 99%

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2010

IEEE Trans. Electron Devices

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Abstract-Program/Erase (P/E) cycling endurance in poly-Si/Al 2 O 3 /SiN/SiO 2 /Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (V FB ) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.

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Highly Reliable Charge Trap‐Type Organic Non‐Volatile Memory Device Using Advanced Band‐Engineered Organic‐Inorganic Hybrid Dielectric Stacks

Kim

Lee

Shin

et al. 2021

Adv Funct Materials

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With the recent interest in data storage in flexible electronics, highly reliable charge trap-type organic-based non-volatile memory (CT-ONVM) has attracted much attention. CT-ONVM should have a wide memory window, good endurance, and long-term retention characteristics, as well as mechanical flexibility. This paper proposed CT-ONVM devices consisting of band-engineered organic-inorganic hybrid films synthesized via an initiated chemical vapor deposition process. The synthesized poly(1,3,5-trimethyl-1,3,5,-trivinyl cyclotrisiloxane) and Al hybrid films are used as a tunneling dielectric layer and a blocking dielectric layer, respectively. For the charge trapping layer, different Hf, Zr, and Ti hybrids are examined, and their memory performances are systematically compared. The best combination of hybrid dielectric stacks showed a wide memory window of 6.77 V, good endurance of up to 10 4 cycles, and charge retention of up to 71% after 10 8 s even under the 2% strained condition. The CT-ONVM device using the hybrid dielectric stacks outperforms other organic-based charge trap memory devices and is even comparable in performance to conventional inorganic-based poly-silicon/oxide/nitride/oxide/silicon structures devices. The CT-ONVM using hybrid dielectrics can overcome the inherent low reliability and process complexity limitations of organic electronics and expedite the realization of wearable organic electronics.

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Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures

Cited by 65 publications

References 4 publications

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Highly Reliable Charge Trap‐Type Organic Non‐Volatile Memory Device Using Advanced Band‐Engineered Organic‐Inorganic Hybrid Dielectric Stacks

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