Electron States in MOS Systems

Abstract

The properties of charge carrier traps in the oxide bulk, at high-k/silicon transition regions, at the silicon interface and as dipoles are discussed from physical and electrical perspectives. In order to elucidate the charging properties of oxide traps the statistical mechanics for occupation is derived based on a constant pressure ensemble and used to interpret the influence of negative-U states. For the transition region close to the silicon interface, the existence of unstable traps in the shift of energy band between SiO2 and HfO2 with continuous modification is pointed out. The physical background for electrical measurements on interface states is examined and, finally, dipoles constituted by traps in high-k dielectrics for regulating threshold voltage of MOS transistors are considered.

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

“…9,22,23) The procedure is repeated until all sub-regions are assigned; thus, the entire IT's density at HfO 2 /Si interface of each device vary from 0:8 Â 10 10 to 6 Â 10 11 eV À1 cm À2 . 24,25,[33][34][35][36] Therefore, 196 randomly generated 3D device samples with 2D random ITs at HfO 2 / Si interface are simulated to assess the influence of ITF.…”

“…[8][9][10][11][12][13][14][15][16][17][18][19] However, emerging fluctuation source, the random interface traps (ITs) at high-/silicon interface degrades device characteristic. [20][21][22][23][24][25][26][27][28][29][30][31] Recently, one-dimensional (1D) and 2D random ITs at high-/silicon interface were proposed for DC characteristic fluctuation simulation of sub-45-nm CMOS devices. 9,16,21) But much less attention has been paid to device's AC and transfer-characteristic fluctuations of a nano-CMOS inverter circuit caused by random ITs.…”